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| rev. 0 aduc832 microconverter , 12-bit adcs and dacs with embedded 62 kbytes flash mcu information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002. all rights reserved. microconverter is a registered tr ademark and qui ckstart is a trademark of analog devices, inc. spi is a registered trademark of motorola, inc. i 2 c is a registered trademark of philips corporation. features analog i/o 8-channel, 247 ksps 12-bit adc dc performance: 1 lsb inl ac performance: 71 db snr dma controller for high speed adc-to-ram capture 2 12-bit (monotonic) voltage output dacs dual output pwm/ - dacs on-chip temperature sensor function 3 c on-chip voltage reference memory 62 kbytes on-chip flash/ee program memory 4 kbytes on-chip flash/ee data memory flash/ee, 100 yr retention, 100 kcycles endurance 2304 bytes on-chip data ram 8051-based core 8051 compatible instruction set (16 mhz max) 32 khz ext crystal, on-chip programmable pll 12 interrupt sources, 2 priority levels dual data pointer extended 11-bit stack pointer on-chip peripherals time interval counter (tic) uart, i 2 c , and spi serial i/o watchdog timer (wdt), power supply monitor (psm) power specified for 3 v and 5 v operation normal, idle, and power-down modes power-down: 25 a @ 3 v with wake-up cct running applications optical networking?aser power control base station systems precision instrumentation, smart sensors transient capture systems das and communications systems upgrade to aduc812 systems. runs from 32 khz external crystal with on-chip pll. also available: aduc831 pin compatible upgrade to existing aduc812 systems that require additional code or data memory. runs from 1 mhz?6 mhz external crystal. functional block diagram 62 kbytes flash/ee program memory 4 kbytes flash/ee data memory 2304 bytes user ram 3 16 bit timers 1 real time clock 4 parallel ports 8051-based mcu with additional peripherals aduc832 xtal2 xtal1 temp sensor v ref internal band gap vref adc0 adc1 adc5 adc6 adc7 osc 12-bit dac dac pwm0 t/h mux 12-bit adc hardware calibraton buf dac buf pwm1 12-bit dac 16-bit dac 16-bit dac 16-bit pwm 16-bit pwm power supply mon watchdog timer uart, i 2 c, and spi serial i/o mux pll general description the aduc832 is a complete smart transducer front end, integrat- ing a high performance self-calibrating multichannel 12-bit adc, dual 12-bit dacs, and programmable 8-bit mcu on a single chip. the device operates from a 32 khz crystal with an on-chip pll generating a high frequency clock of 16.77 mhz. this clock is, in turn, routed through a programmable clock divider from which the mcu core clock operating frequency is generated. the micro- controller core is an 8052 and therefore 8051 instruction set compatible with 12 core clock periods per machine cycle. 62 kbytes of nonvolatile flash/ee program memory are provided on-chip. 4 kbytes of nonvolatile flash/ee data memory, 256 bytes ram, and 2 kbytes of extended ram are also integrated on-chip. the aduc832 also incorporates additional analog functionality with two 12-bit dacs, power supply monitor, and a band gap reference. on-chip digital peripherals include two 16-bit - dacs, dual output 16-bit pwm, watchdog timer, time interval counter, three timers/counters, timer 3 for baud rate generation, and serial i/o ports (spi, i 2 c, and uart) on-chip factory firmware supports in-circuit serial download and debug modes (via uart) as well as single-pin emulation mode via the ea pin. the aduc832 is supported by quickstart ? and quickstart plus development systems featuring low cost software and hardware development tools. a functional block diagram of the aduc832 is shown above with a more detailed block diagram shown in figure 1. the part is specified for 3 v and 5 v operation over the extended industrial temperature range and is available in a 52-lead plastic quad flatpack package and a 56-lead chip scale package.
rev. 0 e2e aduc832 table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . 1 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 absolute maximum ratings . . . . . . . . . . . . . . . 7 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . 8 pin function descriptions . . . . . . . . . . . . . . . . 9 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 typical performance characteristics . . 11 memory organization . . . . . . . . . . . . . . . . . . . 14 overview of mcu-related sfrs . . . . . . . . . . 15 accumulator sfr (acc) . . . . . . . . . . . . . . . . . . . . . . . . . 15 b sfr (b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 stack pointer sfr (sp and sph) . . . . . . . . . . . . . . . . . 15 data pointer (dptr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 program status word sfr (psw) . . . . . . . . . . . . . . . . . . 16 power control sfr (pcon) . . . . . . . . . . . . . . . . . . . . . . 16 special function registers . . . . . . . . . . . . . . 17 adc circuit information . . . . . . . . . . . . . . . . 18 general overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 adc transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . 18 typical operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 adccon1 ? (adc control sfr #1) . . . . . . . . . . . . . . 19 adccon2 ? (adc control sfr #2) . . . . . . . . . . . . . . 20 adccon3 ? (adc control sfr #3) . . . . . . . . . . . . . . 21 driving the a/d converter . . . . . . . . . . . . . . . . . . . . . . . . 22 voltage reference connections . . . . . . . . . . . . . . . . . . . . 23 configuring the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 adc dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 micro operation during adc dma mode . . . . . . . . . . . 25 adc offset and gain calibration coefficients . . . . . . . . 25 calibrating the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 nonvolatile flash memory . . . . . . . . . . . . . . 27 flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . 27 flash/ee memory and the aduc832 . . . . . . . . . . . . . . . 27 aduc832 flash/ee memory reliability . . . . . . . . . . . . . 27 using the flash/ee program memory . . . . . . . . . . . . . . . 28 uload mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 flash/ee program memory security . . . . . . . . . . . . . . . . 28 using the flash/ee data memory . . . . . . . . . . . . . . . . . . 29 econ ? flash/ee memory control sfr . . . . . . . . . . . . 29 flash/ee memory timing . . . . . . . . . . . . . . . . . . . . . . . . 30 aduc832 configuration register (cfg832) . 31 user interface to other on-chip aduc832 peripherals . . . . . . . . . . . . . . . . . . . . . 32 using the dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 on-chip pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 pulsewidth modulator (pwm) . . . . . . . . . . . . . . . . . . . . . 36 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . 39 i 2 c compatible interface . . . . . . . . . . . . . . . . . . . . . . . . . 41 dual data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 power supply monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 timer interval counter . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8052 compatible on-chip peripherals . . . . 48 parallel i/o ports 0 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 timers/counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 uart serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 uart serial port control register . . . . . . . . . . . . . . . . . 56 uart operating modes . . . . . . . . . . . . . . . . . . . . . . . . . 57 uart serial port baud rate generation . . . . . . . . . . . . 57 timer 1 generated baud rates . . . . . . . . . . . . . . . . . . . . 58 timer 2 generated baud rates . . . . . . . . . . . . . . . . . . . . 58 timer 3 generated baud rates . . . . . . . . . . . . . . . . . . . . 59 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 aduc832 hardware design considerations . 61 clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 external memory interface . . . . . . . . . . . . . . . . . . . . . . . 62 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 grounding and board layout recommendations . . . . . . 64 other hardware considerations . . . . . . . . 65 in-circuit serial download access . . . . . . . . . . . . . . . . . 65 embedded serial port debugger . . . . . . . . . . . . . . . . . . . 66 single-pin emulation mode . . . . . . . . . . . . . . . . . . . . . . . 66 typical system configuration . . . . . . . . . . . . . . . . . . . . . 66 development tools . . . . . . . . . . . . . . . . . . . . . . 66 timing specifications . . . . . . . . . . . . . . . . . . . . 67 outline dimensions . . . . . . . . . . . . . . . . . . . . . . 77 rev. 0 e3e (av dd = dv dd = 2.7 v to 3.3 v or 4.5 v to 5.5 v; v ref = 2.5 v internal reference, f core =16.78 mhz; all specifications t a = t min to t max , unless otherwise noted.) parameter v dd = 5 v v dd = 3 v unit test conditions/comments adc channel specifications dc accuracy 2, 3 f sample = 147 khz, see page 11 for typical performance at other f sample resolution 12 12 bits integral nonlinearity + + , = = () () = ?, = = = ? rev. 0 e4e aduc832 specifications (continued) parameter v dd = 5 v v dd = 3 v unit test conditions/comments dac channel specifications 12, 13 internal buffer disabled dc accuracy 10 resolution 12 12 bits relative accuracy = ( ) ( ) ? () () , , ( ) ( ) ( , ) = = ( ) = = ( , , ) = ( , ) = = rev. 0 aduc832 e5e parameter v dd = 5 v v dd = 3 v unit test conditions/comments sclock and reset only 4 (schmitt-triggered inputs) v t+ 1.3 0.95 v min 3.0 2.5 v max v t ? 0.8 0.4 v min 1.4 1.1 v max v t+ ? v t ? 0.3 0.3 v min 0.85 0.85 v max crystal oscillator logic inputs, xtal1 only v inl , input low voltage 0.8 0.4 v typ v inh , input high voltage 3.5 2.5 v typ xtal1 input capacitance 18 18 pf typ xtal2 output capacitance 18 18 pf typ mcu clock rate 16.78 16.78 mhz max programmable via pllcon digital outputs output high voltage (v oh ) 2.4 v min v dd = 4.5 v to 5.5 v 4.0 v typ i source = 80 = = ( ) , = = = = , rev. 0 e6e aduc832 notes 1 temperature range ? 40 o c to +125 o c. 2 adc linearity is guaranteed during normal microconverter core operation. 3 adc lsb size = v ref /2 12 i.e., for internal v ref = 2.5 v, 1 lsb = 610 = , = , , , = ? , , , , , , + , + , ( ) = , , = , = , , = , = , , = , = , = , , , = , , () ( ) ( ) = = , = = = = = = = = = = = = = = = () rev. 0 aduc832 e7e caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the aduc832 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * (t a = 25 , ) + + , + + + + + + + + ? () ? () , ( ) ( ) + + rev. 0 C8C aduc832 pin configuration watchdog timer 256 bytes user ram power supply monitor temp sensor band gap reference av dd agnd dv dd dv dd dv dd dgnd dgnd dgnd reset por sdata/mosi miso ss xtal1 aduc832 adc control and calibration dac1 dac control 12-bit voltage output dac t0 t1 t2ex t2 int0 int1 ea psen ale single-pin emulator txd rxd 4 kbytes data flash/ee 62 kbytes program flash/ee including user download mode asynchronous serial port ( uart) 8052 mcu core downloader debugger synchronous serial interface ( spi or i 2 c ) 16-bit counter timers time interval counter ( wakeup cct) xtal2 osc 2 kbytes user xram 2 data pointers 11-bit stack pointer 12-bit voltage output dac mux ... ... 12-bit adc adc0 adc1 adc6 adc7 dac0 mux pwm0 pwm1 16-bit pwm 16-bit pwm pwm control t/h v ref c ref buf uart timer prog. clock divider pll sclock 16-bit - dac 16-bit - dac figure 1. aduc832 block diagram (shaded areas are features not present on the aduc812) 52 51 50 49 48 43 42 41 40 47 46 45 44 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 13 12 11 39 38 37 36 35 34 33 32 31 30 29 28 27 pin 1 identifier top view (not to scale) p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 dv dd dgnd p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 ale psen ea p1.0/adc0/t2 p1.1/adc1/t2ex p1.2/adc2 p1.3/adc3 av dd agnd c ref v ref dac0 dac1 p1.4/adc4 p1.5/adc5/ ss p1.6/adc6 p2.7/pwm1/a15/a23 p2.6/pwm0/a14/a22 p2.5/a13/a21 p2.4/a12/a20 dgnd dv dd xtal2 xtal1 p2.3/a11/a19 p2.2/a10/a18 p2.1/a9/a17 p2.0/a8/a16 sdata/mosi p1.7/adc7 reset p3.0/rxd p3.1/txd p3.2 /int0 p3.3 /int1 /miso/pwm1 dv dd dgnd p3.4/t0/pwmc/pwm0/extclk p3.5/t1/ convst p3.7/ rd sclock p3.6/ wr aduc832 52-lead pqfp p1.1/adc1/t2ex p 1.2/adc2 p1.3/adc3 av dd av dd agnd agnd agnd c ref v ref dac0 dac1 p1.4/adc4 p1.5/adc5/ ss p1.6/adc6 p.7/adc7 reset p3.0/rxd p3.1/txd p3.3 /int1 /miso/pwm1 p3.2 /int0 dv dd dgnd p3.4/t0/pwmc/pwm0/extclk p3.5/t1/ convst p3.6/ wr p3.7/ rd sclock p2.7/pwm1/a15/a23 p2.6/pwm0/a14/a22 p2.5/a13/a21 p2.4/a12/a20 dgnd dgnd dv dd xtal1 p2.3/a11/a19 p2.2/a10/a18 p2.1/a9/a17 p2.0/a8/a16 sdata/mosi p1.0/adc0/t2 p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 dv dd dgnd p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 ale psen ea 14 1 2 3 4 5 6 7 8 9 10 11 13 12 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 43 45 46 47 48 49 50 51 52 53 54 55 56 pin 1 identifier 44 aduc832 56-lead csp top view (not to scale) xtal2 rev. 0 aduc832 e9e pin function descriptions mnemonic type function dv dd pd igital positive supply voltage, 3 v or 5 v nominal av dd pa nalog positive supply voltage, 3 v or 5 v nominal c ref i/o decoupling input for on-chip reference. connect 0.1 , , , , , , , () () () () () () , , , , , , ( ) , , ( ) rev. 0 e10e aduc832 pin function descriptions (continued) mnemonic type function psen op rogram store enable, logic output. this output is a control signal that enables the external program memory to the bus during external fetch operations. it is active every six oscillator periods except during external data memory accesses. this pin remains high during internal program execution. psen can also be used to enable serial download mode when pulled low through a resistor on power-up or reset. ale o address latch enable, logic output. this output is used to latch the low byte (and page byte for 24-bit address space accesses) of the address into external memory during normal operation. it is activated every six oscillator periods except during an external data memory access. ea ie xternal access enable, logic input. when held high, this input enables the device to fetch code from internal program memory locations 0000h to 1fffh. when held low, this input enables the device to fetch all instructions from external program memory. this pin should not be left floating. p0.7 ? p0.0 i/o port 0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1s written to them float and in (a0 ? a7) that state can be used as high impedance inputs. port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory. in this application it uses strong internal pull-ups when emitting 1s. terminology adc specifications integral nonlinearity this is the maximum deviation of any code from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1/2 lsb below the first code transition, and full scale, a point 1/2 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, i.e., +1/2 lsb. gain error this is the deviation of the last code transition from the ideal ain voltage (full scale ? 1.5 lsb) after the offset error has been adjusted out. signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the rms sum of all nonfundamental sig- nals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to(noise distortion)= (6.02n + 1.76) db + , rev. 0 t ypical performance characteristicseaduc832 e11e the typical performance plots presented in this section illustrate typical performance of the aduc832 under various operating conditions. tpc 1 and tpc 2 show typical adc integral nonlinearity (inl) errors from adc code 0 to code 4095 at 5 v and 3 v supplies, respectively. the adc is using its internal reference (2.5 v) and operating at a sampling rate of 152 khz and the typically worst case errors in both plots are just less than 0.3 lsbs. tpc 3 and tpc 4 show the variation in worst case positive (wcp) inl and worst case negative (wcn) inl versus external reference input voltage. tpc 5 and tpc 6 show typical adc differential nonlinearity (dnl) errors from adc code 0 to code 4095 at 5 v and 3 v supplies, respectively. the adc is using its internal reference (2.5 v) and operating at a sampling rate of 152 khz and the typically worst case errors in both plots is just less than 0.2 lsbs. tpc 7 and tpc 8 show the variation in worst case positive (wcp) dnl and worst case negative (wcn) dnl versus external reference input voltage. tpc 9 shows a histogram plot of 10,000 adc conversion results on a dc input with v dd = 5 v. the plot illustrates an excellent code distribution pointing to the low noise performance of the on-chip precision adc. adc codes e1.0 0 511 lsbs 1023 2047 2559 3071 e0.8 1535 3583 e0.6 e0.4 e0.2 0 0.2 0.4 0.6 0.8 1.0 av dd / dv dd = 5v f s = 152khz 4095 tpc 1. typical inl error, v dd = 5 v adc codes 1.0 511 1023 1535 2047 2559 lsbs 0.6 0.2 e0.2 e0.6 e1.0 0.8 0.4 0 e0.4 e0.8 3071 3583 0 4095 av dd /dv dd = 3v f s = 152khz tpc 2. typical inl error, v dd = 3 v external reference e v 1.2 wcpeinl e lsbs 0.8 0.4 0 e0.4 e0.6 1.0 0.6 0.2 e0.2 av dd /dv dd = 5v f s = 152khz 0.5 1.0 1.5 2.0 2.5 5.0 0.6 0.4 0 e0.4 e0.6 0.2 e0.2 wcneinl e lsbs wcn inl wcp inl tpc 3. typical worst case inl error vs. v ref , v dd = 5 v external reference e v wcpeinl e lsbs 0.8 0.4 0 e0.4 e0.8 0.6 0.2 e0.2 av dd /dv dd = 3v f s = 152khz 0.5 1.5 2.5 wcneinl e lsbs e0.6 0.8 0.4 0 e0.4 e0.8 0.6 0.2 e0.2 e0.6 3.0 2.0 1.0 wcn inl wcp inl tpc 4. typical worst case inl error vs. v ref , v dd = 3 v tpc 10 shows a histogram plot of 10,000 adc conversion results on a dc input for v dd = 3 v. the plot again illustrates a very tight code distribution of 1 lsb with the majority of codes appearing in one output pin. tpc 11 and tpc 12 show typical fft plots for the aduc832. these plots were generated using an external clock input. the adc is using its internal reference (2.5 v) sampling a full-scale, 10 khz sine wave test tone input at a sampling rate of 149.79 khz. the resultant ffts shown at 5 v and 3 v supplies illustrate an excellent 100 db noise floor, 71 db signal-to-noise ratio (snr) and thd greater than ? 80 db. tpc 13 and tpc 14 show typical dynamic performance versus external reference voltages. again, excellent ac performance can be observed in both plots with some roll-off being observed as v ref falls below 1 v. tpc 15 shows typical dynamic performance versus sampling frequency. snr levels of 71 dbs are obtained across the sampling range of the aduc832. tpc 16 shows the voltage output of the on-chip temperature sensor versus temperature. although the initial voltage output at 25 o c can vary from part to part, the resulting slope of ? 2 mv/ o c is constant across all parts. rev. 0 e12e aduc832 external reference e v wcpednl e lsbs 0.7 0.5 0.1 e0.5 e0.7 0.3 e0.3 av dd /dv dd = 3v f s = 152khz 0.5 1.0 1.5 2.0 2.5 3.0 wcnednl e lsbs wcp dnl wcn dnl e0.1 0.7 0.5 0.1 e0.5 e0.7 0.3 e0.3 e0.1 tpc 8. typical worst case dnl error vs. v ref , v dd = 3 v code 817 818 819 820 821 10000 occurrence 8000 6000 4000 2000 0 tpc 9. code histogram plot, v dd = 5 v code 10000 817 818 819 820 821 occurrence 8000 6000 4000 2000 0 9000 7000 5000 3000 1000 tpc 10. code histogram plot, v dd = 3 v adc codes 1.0 511 1023 1535 2047 2559 lsbs 0.6 0.2 e0.2 e0.6 e1.0 0.8 0.4 0 e0.4 e0.8 3071 3583 0 4095 av dd /dv dd = 5v f s = 152khz tpc 5. typical dnl error, v dd = 5 v adc codes 1.0 511 1023 1535 2047 2559 lsbs 0.6 0.2 e0.2 e0.6 e1.0 0.8 0.4 0 e0.4 e0.8 3071 3583 0 4095 av dd /dv dd = 3v f s = 152khz tpc 6. typical dnl error, v dd = 3 v external reference e v e0.6 0.5 wcpednl e lsbs 1.0 2.0 2.5 5.0 e0.4 1.5 e0.2 0 0.2 0.4 0.6 wcnednl e lsbs e0.4 e0.6 e0.2 0 0.2 0.4 0.6 av dd / dv dd = 5v f s = 152khz wcp dnl wcn dnl tpc 7. typical worst case dnl error vs. v ref , v dd = 5 v rev. 0 aduc832 e13e frequency e khz 010 dbs 20 40 50 60 e160 30 70 e140 e120 e100 e80 e60 e40 e20 0 20 av dd / dv dd = 5v f s = 152khz f in = 9.910khz snr = 71.3db thd = e88.0db enob = 11.6 tpc 11. dynamic performance at v dd = 5 v frequency e khz 010 dbs 20 40 50 60 e160 30 70 e140 e120 e100 e80 e60 e40 e20 0 20 av dd / dv dd = 3v f s = 149.79khz f in = 9.910khz snr = 71.0db thd = e83.0db enob = 11.5 tpc 12. dynamic performance at v dd = 3 v external reference e v 50 0.5 snr e dbs 1.0 2.0 2.5 5.0 55 1.5 60 65 70 75 80 thd e dbs e100 e95 e90 e85 e80 e75 e70 av dd / dv dd = 5v f s = 152khz snr thd tpc 13. typical dynamic performance vs. v ref , v dd = 5 v external reference e v snr e dbs 80 75 65 50 70 55 av dd /dv dd = 3v f s = 152khz 0.5 1.5 2.5 thd e dbs snr thd 60 e70 e75 e85 e100 e80 e95 e90 1.0 2.0 3.0 tpc 14. typical dynamic performance vs. v ref , v dd = 3 v frequency e khz 64 92.262 snr e dbs 119.05 172.62 199.41 226.19 66 145.83 68 70 72 76 80 av dd / dv dd = 5v 78 74 62 60 65.476 tpc 15. typical dynamic performance vs. sampling frequency temperature e c 0.40 e40 voltage e v e20 0.45 0.50 0.55 0.60 0.70 0.80 0.75 0.65 av dd / dv dd = 3v slope = 2mv/ c 0 25 50 85 tpc 16. typical temperature sensor output vs. temperature rev. 0 e14e aduc832 memory organization the aduc832 contains four different memory blocks: 62 kbytes of on-chip flash/ee program memory 4 kbytes of on-chip flash/ee data memory 256 bytes of general-purpose ram 2 kbytes of internal xram flash/ee program memory the aduc832 provides 62 kbytes of flash/ee program memory to run user code. the user can choose to run code from this internal memory or from an external program memory. if the user applies power or resets the device while the ea pin is pulled low, the part will execute code from the external program space; otherwise the part defaults to code execution from its internal 62 kbytes of flash/ee program memory. unlike the aduc812, where code execution can overflow from the internal code space to external code space once the pc becomes greater than 1fffh, the aduc832 does not support the rollover from f7ffh in internal code space to f800h in external code space. instead the 2048 bytes between f800h and ffffh will appear as nop instructions to user code. this internal code space can be downloaded via the uart serial port while the device is in-circuit. 56 kbytes of the program memory can be reprogrammed during runtime; thus the code space can be upgraded in the field using a user defined protocol or it can be used as a data memory. this will be discussed in more detail in the flash/ee memory section. flash/ee data memory 4 kbytes of flash/ee data memory are available to the user and can be accessed indirectly via a group of control registers mapped into the special function register (sfr) area. access to the flash/ee data memory is discussed in detail later as part of the flash/ee memory section. general-purpose ram the general-purpose ram is divided into two separate memories, namely the upper and the lower 128 bytes of ram. the lower 128 bytes of ram can be accessed through direct or indirect addressing. the upper 128 bytes of ram can only be acc essed through indirect addressing as it shares th e same address space as the sfr space, which can only be accessed through direct addressing. the lower 128 bytes of internal data memory are mapped as shown in figure 2. the lowest 32 bytes are grouped into four banks of eight registers addressed as r0 through r7. the next 16 bytes (128 bits), locations 20h through 2fh above the register banks, form a block of directly addressable bit locations at bit addresses 00h through 7fh. the stack can be located anywhere in the internal memory address space, and the stack depth can be expanded up to 2048 bytes. reset initializes the stack pointer to location 07h and increments it once before loading the stack to start from locations 08h which is also the first register (r0) of register bank 1. thus, if one is going to use more than one register bank, the stack pointer should be initialized to an area of ram not used for data storage. bit-addressable (bit addresses) four banks of eight registers r0 r7 banks selected via bits in psw 11 10 01 00 07h 0fh 17h 1fh 2fh 7fh 00h 08h 10h 18h 20h reset value of stack pointer 30h general-purpose area figure 2. lower 128 bytes of internal data memory the aduc832 contains 2048 bytes of internal xram, 1792 bytes of which can be configured to be used as an extended 11-bit stack pointer. by default, the stack will operate exactly like an 8052 in that it will roll over from ffh to 00h in the general-purpose ram. on the aduc832, however, it is possib le (by se tting cf g 832.7) to enable the 11-bit extended stack pointer. in this case, the stack will roll over from ffh in ram to 0100h in xram. the 11-bit stack pointer is visible in the sp and sph sfrs. the sp sfr is located at 81h as with a standard 8052. the sph sfr is located at b7h. the 3 lsbs of this sfr contain the three extra bits necessary to extend the 8-bit stack pointer into an 11-bit stack pointer. upper 1792 bytes of on-chip xram (data + stack for exsp = 1, data only for exsp = 0) 256 bytes of on-chip data ram (data + stack) lower 256 bytes of on-chip xram (data only) 00h ffh 00h 07ffh cfg832.7 = 0 cfg832.7 = 1 100h figure 3. extended stack pointer operation rev. 0 aduc832 e15e external data memory (external xram) just like a standard 8051 compatible core, the aduc832 can access external data memory using a movx instruction. the movx instruction automatically outputs the various control strobes required to access the data memory. the aduc832, however, can access up to 16 mbytes of external data memory. this is an enhancement of the 64 kbytes external data memory space available on a standard 8051 compatible core. the external data memory is discussed in more detail in the aduc832 hardware design considerations section. internal xram 2 kbytes of on-chip data memory exist on the aduc832. this memory, although on-chip, is also accessed via the movx instruction. the 2 kbytes of internal xram are mapped into the bottom 2 kbytes of the external address space if the cfg832 bit is set. otherwise, access to the external data memory will occur just like a standard 8051. when using the internal xram, ports 0 and 2 are free to be used as general-purpose i/o. external data memory space (24-bit address space) 000000h ffffffh cfg832.0 = 0 external data memory space (24-bit address space) 000000h ffffffh cfg832.0 = 1 0007ffh 000800h 2 kbytes on-chip xram figure 4. internal and external xram special function registers (sfrs) the sfr space is mapped into the upper 128 bytes of internal data memory space and accessed by direct addressing only. it provides an interface between the cpu and all on chip periph- erals. a block diagram showin g the programming model of the aduc832 via the sfr area is shown in figure 5. all registers, except the program counter (pc) and the four general- purpose register banks, reside in the sfr area. the sfr registers include control, configuration, and data registers that provide an interface between the cpu and all on-chip peripherals. 128-byte special function register area 62-kbyte electrically reprogrammable nonvolatile flash/ee program memory 8051 compatible core other on-chip peripherals temperature sensor 2 12-bit dacs serial i/o wdt psm tic pwm 8-channel 12-bit adc 4-kbyte electrically reprogrammable nonvolatile flash/ee data memory 2304 bytes ram figure 5. programming model accumulator sfr (acc) acc is the accumulator register and is used for math opera tions including addition, subtraction, integer multiplication and divi sion, and boolean bit manipulations. the mnemonics for accumula tor- specific instructions refer to the accumulator as a. b sfr (b) the b register is used with the acc for multiplication and divi- sion operations. for other instructions, it can be treated as a general-purpose scratch pad register. stack pointer (sp and sph) the sp sfr is the stack pointer and is used to hold an internal ram address that is called the top of the stack. the sp register is incremented before data is stored during push and call execu- tions. while the stack may reside anywhere in on-chip ram, the sp register is initialized to 07h after a reset. this causes the stack to begin at location 08h. as mentioned earlier, the aduc832 offers an extended 11-bit stack pointer. the three ex tra bits to make up the 11-bit stack pointer are the 3 lsbs of the sph byte located at b7h. rev. 0 e16e aduc832 data pointer (dptr) the data pointer is made up of three 8-bit registers, named dpp (page byte), dph (high byte) and dpl (low byte). these are used to provide memory addresses for internal and external code access and external data access. it may be manipulated as a 16-bit register (dptr = dph, dpl), although inc dptr instructions will automatically carry over to dpp, or as three independent 8-bit registers (dpp, dph, dpl). the aduc832 supports dual data pointers. refer to the dual data pointer section. program status word (psw) the psw sfr contains several bits reflecting the current status of the cpu as detailed in table i. sfr address d0h power-on default value 00h bit addressable yes table i. psw sfr bit designations bit name description 7c yc arry flag 6a ca uxiliary carry flag 5f 0g eneral-purpose flag 4 rs1 register bank select bits 3 rs0 rs1 rs0 selected bank 000 011 102 113 2o vo verflow flag 1f 1g eneral-purpose flag 0p parity bit power control sfr (pcon) the pcon sfr contains bits for power-saving options and general-purpose status flags as shown in table ii. sfr address 87h power-on default value 00h bit addressable no table ii. pcon sfr bit designations bit name description 7 smod double uart baud rate 6 seripd i 2 c/spi power-down interrupt enable 5 int0pd int0 power-down interrupt enable 4 aleoff disable ale output 3 gf1 general-purpose flag bit 2 gf0 general-purpose flag bit 1p d power-down mode enable 0 idl idle mode enable rev. 0 aduc832 e17e spicon 1 f8h 04h dac0l f9h 00h dac0h fah 00h dac1l fbh 00h dac1h fch 00h daccon fdh 04h reserved b 1 f0h 00h adcofsl 3 f1h 00h adcofsh 3 f2h 20h adcgainl 3 f3h 00h adcgainh 3 f4h 00h adccon3 f5h 00h reserved i2ccon 1 e8h 00h reserved acc 1 e0h 00h reserved adccon2 1 d8h 00h adcd atal d9h 00h adcdatah dah 00h reserved psw 1 d0h 00h dmal d2h 00h dmah d3h 00h dmap d4h 00h reserved t2con 1 c8h 00h rcap2l cah 00h rcap2h cbh 00h tl2 cch 00h th2 cdh 00h reserved wdcon 1 c0h 10h ip 1 b8h 00h econ b9h 00h edata1 bch 00h edata2 bdh 00h ie 1 a8h 00h ieip2 a9h a0h p2 1 a0h ffh scon 1 98h 00h sbuf 99h 00h i2cdat 9ah 00h not used p1 1, 2 90h ffh not used tcon 1 88h 00h tmod 89h 00h tl0 8ah 00h tl1 8bh 00h th0 8ch 00h th1 8dh 00h p0 1 80h ffh sp 81h 07h dpl 82h 00h dph 83h 00h dpp 84h 00h reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved not used not used not used p3 1 b0h ffh not used not used not used not used not used spidat f7h 00h adccon1 efh 00h reserved psmcon dfh deh edarl c6h 00h edata3 beh 00h edata4 bfh 00h not used pcon 87h 00h ispi ffh 0 wcol feh 0 spe fdh 0 spim fch 0 cpol fbh 0 cpha fah spr1 f9h 0 spr0 f8h 0 bits f7h 0 f6h 0 f5h 0 f4h 0 f3h 0 f2h f1h 0 f0h 0 bits mdo efh 0 eeh 0 mco edh 0 ech 0 ebh 0 eah e9h 0 e8h 0 bits e7h 0 e6h 0 e5h 0 e4h 0 e3h 0 e2h e1h 0 e0h 0 bits adci dfh 0 dma deh 0 cconv ddh 0 sconv dch 0 cs3 dbh 0 cs2 dah cs1 d9h 0 cs0 d8h 0 bits cy d7h 0 ac d6h 0 f0 d5h 0 rs1 d4h 0 rs0 d3h 0 ov d2h fi d1h 0 p d0h 0 bits tf2 cfh 0 exf2 ceh 0 rclk cdh 0 tclk cch 0 exen2 cbh 0 tr2 cah cnt2 c9h 0 cap2 c8h 0 bits pre3 c7h 0 pre2 c6h 0 pre1 c5h 0 c4h 1 wdir c3h 0 wds c2h wde c1h 0 wdwr c0h 0 bits psi bfh 0 padc beh 0 pt2 bdh 0 ps bch 0 pt1 bbh 0 px1 bah pt0 b9h 0 px0 b8h 0 bits rd b7h 1 wr b6h 1 t1 b5h 1 t0 b4h 1 int1 b3h 1 int0 b2h txd b1h 1 rxd b0h 1 bits ea afh eadc aeh et2 adh es ach 0 et1 abh 0 ex1 aah et0 a9h 0 ex0 a8h 0 bits a7h a6h a5h 1 a4h 1 a3h 1 a2h a1h 1 a0h 1 bits sm0 9fh 0 sm1 9eh 0 sm2 9dh 0 ren 9ch 0 tb8 9bh 0 rb8 9ah ti 99h 0 ri 98h 0 bits 97h 1 96h 1 95h 1 94h 1 93h 1 92h t2ex 91h 1 t2 90h 1 bits tf1 8fh 0 tr1 8eh 0 tf0 8dh 0 tr0 8ch 0 ie1 8bh 0 it1 8ah ie0 89h 0 it0 88h 0 bits 87h 1 86h 1 85h 1 84h 1 83h 1 82h 81h 1 80h 1 bits 1 1 0 1 0 1 ie0 89h 0 it0 88h 0 tcon 88h 00h mnemonic sfr address default value mnemonic default value sfr address these bits are contained in this byte. sfr map key: notes 1 sfrs whose address ends in 0h or 8h are bit addressable. 2 the primary function of port1 is as an analog input port; therefore, to enable the digital secondary functions on these port pins, write a 0 to the corresponding port 1 sfr bit. 3 calibration coefficients are preconfigured on power-up to factory calibrated values. 1 reserved reserved reserved 0 0 0 0 0 0 0 0 0 0 0 0 11 timecon hthsec sec min hour intval dpcon a1h a2h a3h a4h a5h a6h a7h 00h 00h 00h 00h 00h 00h 00h reserved reserved reserved reserved reserved reserved pwmcon aeh 00h cfg832 afh 00h reserved reserved t3fd t3con 9dh 9eh 00h 00h pwm0l pwm0h pwm1l pwm1h sph 00h 00h 00h 00h 00h b1h b2h b3h b4h b7h reserved reserved reserved chipid c2h 2xh edarh c7h 00h mde i2cm reserved pre0 pllcon d7h 53h mdi i2crs i2ctx i2ci i2cadd 9bh 55h figure 6. special function register locations and reset values special function registers all registers except the program counter and the four general- purpose register banks reside in the special function register (sfr) area. the sfr registers include control, configuration, and data registers that provide an interface between the cpu and other on-chip peripherals. figure 6 shows a full sfr memory map and sfr contents on reset. unoccupied sfr locations are shown dark-shaded in the figure below (not used). unoccupied locations in the sfr address space are not implemented i.e., no register exists at this location. if an unoccupied location is read, an unspecified value is returned. sfr locations reserved for on-chip testing are shown lighter shaded below (reserved) and should not be accessed by user software. sixteen of the sfr locations are also bit addressable and denoted by '1' in the figure below, i.e., the bit addressable sfrs are those whose address ends in 0h or 8h. rev. 0 e18e aduc832 adc circuit information general overview the adc conversion block incorporates a fast, 8-channel, 12-bit, single-supply adc. this block provides the user with multichannel mux, track/hold, on-chip reference, calibration features, and adc. all components in this block are easily configured via a 3-register sfr interface. t he adc converter consists of a conventional successive- a pproximation converter based around a capacitor dac. the converter accepts an analog input range of 0 to v ref . a high precision, low drift, and factory calibrated 2.5 v reference is provided on-chip. an external reference can be connected as described later. this external reference can be in the range 1 v to av dd . single step or continuous conversion modes can be initiated in software or alternatively by applying a convert signal to an e xternal pin. timer 2 can also be configured to generate a repeti- tiv e trigger for adc conversions. the adc may be configured to operate in a dma mode whereby the adc block continu- ously converts and captures samples to an external ram space without any interaction from the mcu core. this automatic capture facility can extend through a 16 mbyte external data memory space. the aduc832 is shipped with factory programmed calibration coefficients that are automatically downloaded to the adc on power-up, ensuring optimum adc performance. the adc core contains internal offset a nd gain calibra tion reg isters that can be hardware calibrated to minimize system errors. a voltage output from an on-chip band gap reference propor- tional to absolute temperature can also be routed through the front end adc multiplexer (effectively a ninth adc channel input) facilitating a temperature sensor implementation. adc transfer function the analog input range for the adc is 0 v to v ref . for this r ange, the designed code transitions occur midway between successive integer lsb values (i.e., 1/2 lsb, 3/2 lsbs, 5/2 ls bs . . . fs ? 3/2 lsbs). the output coding is straight binary with 1 lsb = fs/4096 or 2.5 v/4096 = 0.61 mv when v ref = 2.5 v. the ideal input/output transfer characteristic for the 0 to v ref range is shown in figure 7. output code 111...111 111...110 111...101 111...100 000...011 000...010 000...001 000...000 0v 1lsb +fs e1lsb voltage input 1lsb = fs 4096 figure 7. adc transfer function typical operation once configured via the adccon 1-3 sfrs, the adc will con- vert the analog input and provide an adc 12-bit result word in the adcdatah/l sfrs. the top four bits of the adcdatah sfr will be written with the channel selection bits so as to identify the channel result. the format of the adc 12-bit result word is shown in figure 8. cheid top 4 bits high 4 bits of adc result word low 8 bits of the adc result word adcdatah sfr adcdatal sfr figure 8. adc result format rev. 0 aduc832 e19e table iii. adccon1 sfr bit designations bit name description adccon1.7 md1 the mode bit selects the active operating mode of the adc. set by the user to power up the adc. cleared by the user to power down the adc. adccon1.6 ext_ref set by the user to select an external reference. cleared by the user to use the internal reference. adccon1.5 ck1 the adc clock divide bits (ck1, ck0) select the divide ratio for the pll master clock used to generate the adccon1.4 ck0 adc clock. to ensure correct adc operation, the divider ratio must be chosen to reduce the adc clock to 4.5 mhz and below. a typical adc conversion will require 17 adc clocks. the divider ratio is selected as follows: ck1 ck0 mclk divider 008 014 1016 1132 adccon1.3 aq1 the adc acquisition select bits (aq1, aq0) select the time provided for the input track-and-hold amplifier adccon1.2 aq0 to acquire the input signal. an acquisition of three or more adc clocks is recommended; clocks are selected as follows: aq1 aq0 #adc clks 001 012 103 114 adccon1.1 t2c the timer 2 conversion bit (t2c) is set by the user to enable the timer 2 overflow bit be used as the adc convert start trigger input. adccon1.0 exc the external trigger enable bit (exc) is set by the user to allow the external pin p3.5 (convst) to be used as the active low convert start input. this input should be an active low pulse (minimum pulsewidth >100 ns) at the required sample rate. adccon1 e (adc control sfr #1) the adccon1 register controls conversion and acquisition times, hardware conversion modes, and power-down modes as detailed below. sfr address: efh sfr power-on default value: 00h bit addressable: no rev. 0 e20e aduc832 table iv. adccon2 sfr bit designations bit name description adccon2.7 adci the adc interrupt bit (adci) is set by hardware at the end of a single adc conversion cycle or at the end of a dma block conversion. adci is cleared by hardware when the pc vectors to the adc interrupt service routine. otherwise, the adci bit should be cleared by user code. adccon2.6 dma the dma mode enable bit (dma) is set by the user to enable a preconfigured adc dma mode opera- tion. a more detailed description of this mode is given in the adc dma mode section. the dma bit is automatically set to ? 0 ? at the end of a dma cycle. setting this bit causes the ale output to cease, it will start again when dma is started and will operate correctly after dma is complete. adccon2.5 cconv the continuous conversion bit (cconv) is set by the user to initiate the adc into a continuous mode of conversion. in this mode, the adc s tarts converting based on the tim ing and channel configuration al r eady set up in the a dccon sfrs; the adc automatically starts another conversion once a previ- ous conversion has completed. adccon2.4 sconv the single conversion bit (sconv) is set to initiate a single conversion cycle. the sconv bit is automatically reset to ? 0 ? on completion of the single conversion cycle. adccon2.3 cs3 the channel selection bits (cs3 ? 0) allow the user to program the adc channel selection under adccon2.2 cs2 software control. when a conversion is initiated, the channel converted will be that pointed to by adccon2.1 cs1 these channel selection bits. in dma mode, the channel selection is derived from the channel id adccon2.0 cs0 written to the external memory. cs3 cs2 cs1 cs0 ch# 00000 00011 00102 00113 01004 01015 01106 01117 1000t emp monitor requires minimum of 1 , ( ) rev. 0 aduc832 e21e adccon3 e (adc control sfr #3) the adccon3 register controls the operation of various calibra- tion m odes as well as giving an indication of adc busy status. sfr address: f5h sfr power-on default value: 00h bit addressable: no table v. adccon3 sfr bit designations bit name description adccon3.7 busy the adc busy status bit (busy) is a read-only status bit that is set during a valid adc conversion or calibration cycle. busy is automatically cleared by the core at the end of conversion or calibration. adccon3.6 gncld gain calibration disable bit. set to ? 0 ? to enable gain calibration. set to ? 1 ? to disable gain calibration. adccon3.5 avgs1 number of averages selection bits. adccon3.4 avgs0 this bit selects the number of adc readings averaged during a calibration cycle. avgs1 avgs0 number of averages 0 0 15 0 1 1 1 0 31 1 1 63 adccon3.3 rsvd reserved. this bit should always be written as ? 0. ? adccon3.2 rsvd this bit should always be written as ? 1 ? by the user when performing calibration. adccon3.1 typical calibration type select bit. this bit selects between offset (zero-scale) and gain (full-scale) calibration. set to ? 0 ? for offset calibration. set to ? 1 ? for gain calibration. adccon3.0 scal start calibration cycle bit. when set, this bit starts the selected calibration cycle. it is automatically cleared when the calibration cycle is completed. rev. 0 e22e aduc832 driving the a/d converter the adc incorporates a successive approximation (sar) archi- tecture involving a charge-sampled input stage. figure 9 shows the equivalent circuit of the analog input section. each adc conversion is divided into two distinct phases as defined by the position of the switches in figure 9. during the sampling phase (with sw1 and sw2 in the ? track ? position) a charge propor- tional to the voltage on the analog input is developed across the input sampling capacitor. during the conversion phase (with both switches in the ? hold ? position) the capacitor dac is adjusted via internal sar logic until the voltage on node a is zero, indicating that the sampled charge on the input capacitor is balanced out by the charge being output by the capacitor dac. the digital value finally contained in the sar is then latched out as the result of the adc conversion. control of the sar, a nd timing of acquisition and sampling modes, is handled a utomatically by built-in adc control logic. acquisition and conversion times are also fully configurable under user control. capacitor dac comparator v ref agnd dac1 dac0 temperature monitor ain7 ain0 32pf agnd aduc832 node a sw1 sw2 track track hold hold 200 200 figure 9. internal adc structure note that whenever a new input channel is selected, a residual charge from the 32 pf sampling capacitor places a transient on the newly selected input. the signal source must be capable of recovering from this transient before the sampling switches click into ? hold ? mode. delays can be inserted in software (between channel selection and conversion request) to account for input stage settling, but a hardware solution will alleviate this burden from the software design task and will ultimately result in a cleaner system implementation. one hardware solution would be to choose a very fast settling op amp to drive each analog input. such an op amp would need to fully settle from a small s ignal transient in less than 300 ns in order to guarantee adequate settling under all software configurations. a better solution, recom- mended for use with any amplifier, is shown in figure 10. though at first glance the circuit in figure 10 may look like a simple antialiasing filter, it actually serves no such purpose since its corner frequency is well above the nyquist frequency, even at a 200 khz sample rate. though the r/c does help to reject some incoming high frequency noise, its primary function is to ensure that the transient demands of the adc input stage are met. ain0 aduc832 10 0.1 f figure 10. buffering analog inputs it does so by providing a capacitive bank from which the 32 pf sampling capacitor can draw its charge. its voltage will not change by more than one count (1/4096) of the 12-bit transfer function when the 32 pf charge from a previous channel is dumped onto it. a larger capacitor can be used if desired, but not a larger resistor (for reasons described below). the schottky diodes in figure 10 may be necessary to limit the voltage applied to the analog input pin as per the data sheet absolute maximum ratings. they are not necessary if the op amp is powered from the same supply as the aduc832 since in that case the op amp is unable to generate voltages above v dd or below ground. an op amp of some kind is necessary unless the signal source is very low impedance to begin with. dc leakage currents at the aduc832 ? s analog inputs can cause measurable dc errors with external source impedances as little as 100 ? , ? ? = = ? = = , , , , ( ) , , ( , ) , , , , , , , rev. 0 aduc832 e23e ground, no amplifier can deliver signals all the way to ground when powered by a single supply. therefore, if a negative supply is available, you might consider using it to power the front end am plifiers. if you do, however, be sure to include the schottky diodes shown in figure 10 (or at least the lower of the two diodes) to protect the analog input from undervoltage conditions. to summarize this section, use the circuit of figure 10 to drive the analog input pins of the aduc832. voltage reference connections the on-chip 2.5 v band gap voltage reference can be used as the reference source for the adc and dacs. to ensure the accuracy of the voltage reference, you must decouple the v ref pin to ground with a 0.1 , ? ? ? , , , , , , , ( ) , , , , ? ? = = ? , , , ? ? ? rev. 0 e24e aduc832 configuring the adc the aduc832 ? s successive approximation adc is driven by a divided down version of the master clock. to ensure adequate adc operation, this adc clock must be between 400 khz and 6 mhz, and optimum performance is obtained with adc clock between 400 khz and 4.5 mhz. frequencies within this range can easily be achieved with master clock frequencies from 400 khz to well above 16 mhz with the four adc clock divide ratios to choose from. for example, set the adc clock divide ratio to 4 (i.e., adcclk = 16.777216 mhz/8 = 2 mhz) by setting the appropriate bits in adccon1 (adccon1.5 = 0, adccon1.4 = 0). the total adc conversion time is 15 adc clocks, plus 1 adc clock for synchronization, plus the selected acquisition time (1, 2, 3, or 4 adc clocks). for the example above, with a 3-clock acquisition time, total conversion time is 19 adc clocks (or 9.05 ) , , , , ( ) , , , , , , () ( ) ( ) a typical dma mode configuration example to set the aduc832 into dma mode, a number of steps must be followed: 1. the adc must be powered down. this is done by ensuring md1 and md0 are both set to 0 in adccon1. 2. the dma address pointer must be set to the start address of where the adc results are to be written. this is done by writing to the dma mode address pointers dmal, dmah, and dmap. dmal must be written to first, followed by dmah, and then by dmap. 3. the external memory must be preconfigured. this consists of writing the required adc channel ids into the top four bits of every second memory location in the external sram, starting at the first address specified by the dma address pointer. as the adc dma mode operates independent from the aduc832 core, it is necessary to provide it with a stop command. this is done by duplicating the last channel id to be converted followed by ? 1111 ? into the next channel selection field. a typical preconfiguration of external memory is as follows: 11 1 1 00 1 1 00 1 1 100 0 010 1 00 1 0 00000ah 000000h stop command repeat last channel for a valid stop condition convert adc ch#3 convert temp sensor convert adc ch#5 convert adc ch#2 figure 14. typical dma external memory preconfiguration 4. the dma is initiated by writing to the adc sfrs in the following sequence: a. adccon2 is written to enable the dma mode, i.e., mov adccon2, #40h; dma mode enabled. b. adccon1 is written to configure the conversion time and power-up of the adc. it can also enable timer 2 driven conversions or external triggered conversions if required. c. adc conversions are initiated. this is done by starting single conversions, starting timer 2, running for timer 2 conversions, or receiving an external trigger. when the dma conversions are completed, the adc interrupt bit, adci, is set by hardware and the external sram contains the new adc conversion results as shown below. it should be noted that no result is written to the last two memory locations. when the dma mode logic is active, it takes the responsibility of storing the adc results away from both the user and aduc832 core logic. as it writes the results of the adc conversions to exter- na l memory, it takes over the external memory interface from the core. thus, any core instructions that access the external memory while dma mode is enabled will not get access to it. the core will execute the instructions and they will take the same time to execute but they will not gain access to the external memory. no conversion result written here conversion result for adc ch#3 conversion result for temp sensor conversion result for adc ch#5 conversion result for adc ch#2 1111 0011 0011 100 0 010 1 0010 00000ah 000000h stop command figure 15. typical external memory configuration post adc dma operation rev. 0 aduc832 e25e the dma logic operates from the adc clock and uses pipelining to perform the adc conversions and access the external memory at the same time. the time it takes to perform one adc conver- sion is called a dma cycle. the actions performed by the logic during a typical dma cycle are shown in the following diagram. write adc result converted during previous dma cycle read channel id to be converted during next dma cycle convert channel read during previous dma cycle dma cycle figure 16. dma cycle from the previous diagram, it can be seen that during one dma c ycle, the following actions are performed by the dma logic: 1. an adc conversion is performed on the channel whose id was read during the previous cycle. 2. the 12-bit result and the channel id of the conversion per- formed in the previous cycle is written to the external memory. 3. the id of the next channel to be converted is read from external memory. for the previous example, the complete flow of events is shown in figure 16. because the dma logic uses pipelining, it takes three cycles before the first correct result is written out. micro operation during adc dma mode during adc dma mode, the microconverter core is free to continue code execution, including general housekeeping and communication tasks. however, note that mcu core accesses to ports 0 and 2 (which of course are being used by the dma con- troller) are gated ? off ? during adc dma mode of operation. this means that even though the instruction that accesses the external ports 0 or 2 will appear to execute, no data will be seen at these external ports as a result. note that during dma to the internally contained xram, ports 0 and 2 are available for use. the only case in which the mcu will be able to access xram during dma is when the internal xram is enabled and the section of ram to which the dma adc results are being written to lies in an external xram. then the mcu will be able to access the internal xram only. this is also the case for use of the extended stack pointer. the microconverter core can be configured with an interrupt to be triggered by the dma controller when it ha s finished filling the requested block of ram with adc results, allowing the service routine for this interrupt to postprocess data without any real-time timing constraints. adc offset and gain calibration coefficients the aduc832 has two adc calibration coefficients, one for offset calibration and one for gain calibration. both the offset and gain calibration coefficients are 14-bit words, and are each stored in two registers located in the special function register (sfr) area. the offset calibration coefficient is divided into adcofsh (six bits) and adcofsl (eight bits) and the gain calibration coefficient is divided into adcgainh (six bits) and adcgainl (eight bits). the offset calibration coefficient compensates for dc offset errors in both the adc and the input signal. increasing the offset coefficient compensates for positive offset, and effectively pushes the adc transfer function down. decreasing the offset coefficient compensates for negative offset, and effectively pushes the adc transfer function up. the maximum offset that can be compensated is typically , , , , ? ? , () () , , , , () () , , () rev. 0 e26e aduc832 initiating calibration in code when calibrating the adc using adccon1, the adc should be set up into the configuration in which it will be used. the adccon3 register can then be used to set up the device up and calibrate the adc offset and gain. mov adccon1,#0ach ;adc on; adcclk set ;to divide by 16,4 ;acquisition clock to calibrate device offset: mov adccon2,#0bh ;select internal agnd mov adccon3,#25h ;select offset calibration, ;31 averages per bit, ;offset calibration to calibrate device gain: mov adccon2,#0ch ;select internal v ref mov adccon3,#27h ;select offset calibration, ;31 averages per bit, ;offset calibration to calibrate system offset: connect system agnd to an adc channel input (0). mov adccon2,#00h ;select external agnd mov adccon3,#25h ;select offset calibration, ;31 averages per bit to calibrate system gain: connect system v ref to an adc channel input (1). mov adccon2,#01h ;select external v ref mov adccon3,#27h ;select offset calibration, ;31 averages per bit, ;offset calibration the calibration cycle time t cal is calculated by the following equation: t adcclk numav t cal acq = + () , t acq = 4 adcclk, numav = 15, the calibration cycle time is: t t ms cal cal = + = ( ) ( ) , ( ), , wait: mov a, adccon3 ;move adccon3 to a jb acc.7, wait ;if bit 7 is set jump to wait else continue rev. 0 aduc832 e27e nonvolatile flash/ee memory flash/ee memory overview the aduc832 incorporates flash/ee memory technology on-chip to provide the user with nonvolatile, in-circuit, repro- grammable code and data memory space. flash/ee memory is a relatively recent type of nonvolatile memory technology and is based on a single transistor cell architecture. this technology is basically an outgrowth of eprom technology and was developed through the late 1980s. flash/ee memory takes the flexible in-circuit reprogrammable features of eeprom and combines them with the space efficient/density features of eprom (see figure 17). because flash/ee technology is based on a single transistor cell architecture, a flash memory array, like eprom, can be imple- mented to achieve the space efficiencies or memory densities required by a given design. like eeprom, flash memory can be programmed in-system at a byte level, although it must first be erased; the erase being performed in page blocks. thus, flash memory is often and more correctly referred to as flash/ee memory. flash/ee memory technology space efficient/ density in-circuit reprogrammable eprom technology eeprom technology figure 17. flash/ee memory development overall, flash/ee memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit programma- bility, high density, and low cost. incorporated in the aduc832, flash/ee memory technology allows the user to update program code space in-circuit, without the need to replace one-time programmable (otp) devices at remote operating nodes. flash/ee memory and the aduc832 the aduc832 provides two arrays of flash/ee memory for user applications. 62 kbytes of flash/ee program space are provided on-chip to facilitate code execution without any external discrete rom device requirements. the program memory can be pro- grammed in -circuit using the serial download mode provided, using conventional third party memory programmers, or via a user defined protocol that can configure it as data if required. a 4 kbyte flash/ee data memory space is also provided on- chip. this may be used as a general-purpose nonvolatile scratchpad area. user access to this area is via a group of six sfrs. this space can be programmed at a byte level, although it must first be erased in 4-byte pages. aduc832 flash/ee memory reliability the flash/ee program and data memory arrays on the aduc832 are fully qualified for two key flash/ee memory characteristics, namely flash/ee memory cycling endurance and flash/ee memory data retention. endurance quantifies the ability of the flash/ee memory to be cycled through many program, read, and erase cy cles. in real terms, a single endurance cycle is composed of four indepen dent, sequential events. these events are defined as: a. initial page erase sequence b. read/verify sequence a single flash/ee c. byte program sequence memory d. second read/verify sequence endurance cycle in reliability qualification, every byte in both the program and data flash/ee memory is cycled from 00h to ffh until a first fail is recorded, signifying the endurance limit of the on-chip flash/ee memory. as indicated in the specification pages of this data sheet, the aduc832 flash/ee memory endurance qualification has been carried out in accordance with jedec specification a117 over the industrial temperature range of ? 40 + + + , , , , () ( = ) , , , ? = ? rev. 0 ?8 aduc832 using the flash/ee program memory the 62 kbyte flash/ee program memory array is mapped into the lower 62 kbytes of the 64 kbytes program space addressable by the aduc832, and is used to hold user code in typical applications. the program memory flash/ee memory arrays can be programmed in three ways: (1) serial downloading (in-circuit programming) the aduc832 facilitates code download via the standard uart serial port. the aduc832 will enter serial download mode after a reset or power cycle if the psen pin is pulled low through an external 1 k ? resistor. once in serial download mode, the user can download code to the full 62 kbytes of flash/ee program memory while the device is in-circuit in its target appli- cation hardware. a pc serial download executable is provided as part of the aduc832 quickstart development system. the serial download protocol is detailed in a microconverter application note uc004. (2) parallel programming the parallel programming mode is fully compatible with con- ventional third party flash or eeprom device programmers. in this mode, ports p0, p1, and p2 operate as the external data and address bus interface, ale operates as the write enable strobe, and port p3 is used as a general configuration port that configures the device for various program and erase operations during parallel programming. the high voltage (12 v) supply required for flash programming is generated using on-chip charge pumps to supply the high voltage program lines. the complete parallel programming specification is available on the microconverter home page at www.analog.com/microconverter. (3) user download mode (uload) in figure 19 we can see that it was possible to use the 62 kbytes of flash/ee program memory available to the user as one single block of memory. in this mode, all of the flash/ee memory is read only to user code. however, the flash/ee program memory can also be written to during runtime simply by entering uload mode. in uload mode, the lower 56 kbytes of program memory can be erased and reprogrammed by user software as shown in figure 19. uload mode can be used to upgrade your code in the field via any user defined download protocol. configuring the spi port on the aduc832 as a slave, it is possible to completely reprogram the 56 kbytes of flash/ee program memory in only 5 seconds (see uc007). alternatively, uload mode can be used to save data to the 56 kbytes of flash/ee memory. this can be extremely useful in data logging applications where the aduc832 can provide up to 60 kbytes of nv data memory on chip (4 kbytes of dedicated flash/ee data memory also exist). the upper 6 kbytes of the 62 kbytes of flash/ee program memory is only programmable via serial download or parallel programming. this means that this space appears as read only to user code. t herefore, it cannot be accidently erased or repro- grammed by erroneous code execution. this makes it very suitable to use the 6 kbytes as a bootloader. a bootload enable option exists in the serial downloader to always run from e000h after reset. if using a bootloader, this option is recommended to ensure that the bootloader always executes correct code after reset. programming the flash/ee program memory via uload mode is described in more detail in the description of econ and also in technical note uc007. ffffh e000h dfffh 0000h user bootloader space the user bootloader space can be programmed in download/debug mode via the kernel but is read only when executing user code 6 kbyte f800h f7ffh user download space either the download/debug kernel or user code (in uload mode) can program this space. embedded download/debug kernel permanently embedded firmware allows code to be downloaded to any of the 62 kbytes of on-chip program memory. the kernel program appears as 'nop' instructions to user code. 56 kbyte 2 kbyte 62 kbytes of user code memory figure 19. flash/ee program memory map in uload mode flash/ee program memory security the aduc832 facilitates three modes of flash/ee program memory security. these modes can be independently activated, restricting access to the internal code space. these security modes can be enabled as part of serial download protocol as described in technical note uc004 or via parallel programming. the security modes available on the aduc832 are described as follows: lock mode this mode locks the code memory, disabling parallel program- ming of the program memory. however, reading the memory in parallel mode and reading the memory via a movc command from external memory is still allowed. this mode is deactivated by initiating a code-erase command in serial download or parallel programming modes. secure mode this mode locks code in memory, disabling parallel program ming (program and verify/read commands) as well as disabling the execution of a movc instruction from external memory, which is attempting to read the op codes from internal memory. read/write of internal data flash/ee from external memory is also disabled. this mode is deactivated by initiating a code-erase command in serial download or parallel programming modes. serial safe mode this mode disables serial download capability on the device. if serial safe mode is activated and an attempt is made to reset the part into serial download mode, i.e., reset asserted and de-asserted with psen low, the part will interpret the serial download reset as a normal reset only. it will therefore not enter serial dow nload mode but only execute a normal reset sequence. serial safe mode can only be disabled by initiating a code-erase command in parallel programming mode. rev. 0 aduc832 e29e table vii. econ?flash/ee memory commands command description command description econ value (normal mode) (power-on default) (uload mode) 01h results in four bytes in the flash/ee data memory, addressed not implemented. use the movc instruction. read by the page address eadrh/l, being read into edata 1 to 4. 02h results in four bytes in edata1 ? 4 being written to results in bytes 0 ? 255 of internal xram being written write the flash/ee data memory at the page address given to the 256 bytes of flash/ee program memory at the by eadrh/l (0 ) ( ) , , , , , , , ( ) , , ( ) , , , ( ) , , , , () , , , () () () ( ) ( ) ( ) () () () ( ) ( ) ( ) () () () () ( ) ( ) () () ( ) ( ) ( ) ( ) ( ) rev. 0 e30e aduc832 example: programming the flash/ee data memory a user wishes to program f3h into the second byte on page 03h of the flash/ee data memory space while preserving the other three bytes already in this page. a typical program of the flash/ ee data array will involve: 1) setting eadrh/l with the page address 2) writing the data to be programmed to the edata1 ? 4 3) writing the econ sfr with the appropriate command step 1: set up the page address the two address registers eadrh and eadrl hold the high byte address and the low byte address of the page to be addressed. the assembly language to set up the address may appear as: mov eadrh,#0 ; set page address pointer mov eadrl,#03h step 2: set up the edata registers we must now write the four values to be written into the page into the four sfrs edata1 ? 4. unfortunately, we do not know three of them. thus, we must read the current page and over- write the second byte. mov econ,#1 ; read page into edata1-4 mov edata2,#0f3h ; overwrite byte 2 step 3: program page a byte in the flash/ee array can only be programmed if it has previously been erased. to be more specific, a byte can only be programmed if it already holds the value ffh. because of the flash/ee architecture, this erase must happen at a page level; therefore, a minimum of four bytes (one page) will be erased when an erase command is initiated. once the page is erased we can program the four bytes in-page and then perform a verification of the data. mov econ,#5 ; erase page mov econ,#2 ; write page mov econ,#4 ; verify page mov a,econ ; check if econ=0 (ok!) jnz error although the 4 kbytes of flash/ee data memory are shipped from the factory pre-erased, i.e., byte locations set to ffh, it is nonethe less good programming practice to include an erase-all routine as part of any configuration/setup code running on the adu c 832. an erase-all command consists of writing ? 06h ? to the econ sfr, which initiates an erase of the 4 kbyte flash/ee array. this command coded in 8051 assembly w ould appear as: mov econ,#06h ; erase all command ; 2 ms duration flash/ee memory timing typical program and erase times for the aduc832 are as follows: normal mode (operating on flash/ee data memory) readpage (4 bytes) ? 5 machine cycles writepage (4 bytes) ? 380 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) , ( ), , rev. 0 aduc832 e31e aduc832 configuration sfr (cfg832) the cfg832 sfr contains the necessary bits to configure the internal xram, external clock select, pwm output selection, dac buffer, and the extended sp. by default it configures the user into 8051 mode, i.e., extended sp is disabled, internal xram is disabled. cfg832 aduc832 config sfr sfr address afh power-on default value 00h bit addressable no table viii. cfg832 sfr bit designations bit name description 7 exsp extended sp enable . when set to ? 1 ? by the user, the stack will roll over from sph/sp = 00ffh to 0100h. when set to ? 0 ? by the user, the stack will roll over from sp = ffh to sp = 00h. 6 pwpo pwm pin out selection set to ? 1 ? by the user = pwm output pins selected as p3.4 and p3.3. set to ? 0 ? by the user = pwm output pins selected as p2.6 and p2.7. 5 dbuf dac output buffer set to ? 1 ? by the user = dac . output buffer bypassed. set to ? 0 ? by the user = dac output buffer enabled. 4 extclk set by the user to ? 1 ? to select an external clock input on p3.4. set by the user to ? 0 ? to use the internal pll clock. 3 rsvd reserved ? this bit should always contain 0. 2 rsvd reserved ? this bit should always contain 0. 1 rsvd reserved ? this bit should always contain 0. 0 xramen xram enable bit when set to ? 1 ? by the user, the internal xram will be mapped into the lower 2 kbytes of the external address space. when set to ? 0 ? by the user, the internal xram will not be accessible and the external data memory will be mapped into the lower 2 kbytes of external data memory. rev. 0 e32e aduc832 user interface to other on-chip aduc832 peripherals the following section gives a brief overview of the various peripherals also available on-chip. a summary of the sfrs used to control and configure these peripherals is also given. dac the aduc832 incorporates two 12-bit voltage output dacs on-chip. each has a rail-to-rail voltage output buffer capable of driving 10 k ? , ( ) , , , , , , , , = ( ) = = = = = = = = = , = = = = , ( ) ( ) ( ) ( ) , rev. 0 aduc832 e33e using the dac the on-chip dac architecture consists of a resistor string dac followed by an output buffer amplifier, the functional equivalent of which is illustrated in figure 21. details of the actual dac architecture can be found in u.s. patent number 5969657 (www.uspto.gov). features of this architecture include inherent guaranteed monotonicity and excellent differential linearity. output buffer high z disable (from mcu) dac0 r r r r r aduc832 av dd v ref figure 21. resistor string dac functional equivalent as illustrated in figure 21, the reference source for each dac is user selectable in software. it can be either av dd or v ref. in 0-to-av dd mode, the dac output transfer function spans from 0 v to the voltage at the av dd pin. in 0-to-v ref mode, the dac output transfer function spans from 0 v to the internal v ref or, if an external reference is applied, the voltage at the v ref pin. the dac output buffer amplifier features a true rail-to-rail output stage implementation. this means that, unloaded, each output is capable of swinging to within less than 100 mv of both av dd and ground. moreover, the dac ? s linearity specification (when driving a 10 k ? ) except codes 0 to 100, and, in 0-to-av dd mode only, codes 3995 to 4095. linearity degradation near ground and v dd is caused by saturation of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in figure 22. the dotted line in figure 22 indicates the ideal transfer function, and the solid line represents what the transfer function might look like with endpoint nonlinear- ities due to saturation of the output amplifier. note that figure 22 represents a transfer function in 0-to-v dd mode only. in 0-to- v ref mode (with v ref < v dd ) the lower nonlinearity would be similar, but the upper portion of the transfer function would follow the ? ideal ? line right to the end (v ref in this case, not v dd ), showing no signs of endpoint linearity errors. v dd v dd e50mv v dd e100mv 100mv 50mv 0mv 000h fffh figure 22. endpoint nonlinearities due to amplifier saturation the endpoint nonlinearities conceptually illustrated in figure 22 get worse as a function of output loading. most of the aduc832 ? s specifications assume a 10 k ? , () , , , = = , , ( ), = = rev. 0 e34e aduc832 source/sink current e ma 4 0510 15 output voltage e v 3 1 0 dac loaded with 0000h dac loaded with 0fffh figure 24. source and sink current capability with v ref = v dd = 3 v to reduce the effects of the saturation of the output amplifier at values close to ground and to give reduced offset and gain errors, the internal buffer can be bypassed. this is done by setting the dbuf bit in the cfg832 register. this allows a full rail-to-rail output from the dac, which should then be buffered externally using a dual supply op amp in order to get a rail-to-rail output. this external buffer should be located as near as physically possible to the dac output pin on the pcb. note that the unbuffered mode only works in the 0 to v ref range. to drive significant loads with the dac outputs, external buff- ering may be required (even with the internal buffer enabled), as illustrated in figure 25. a list of recommended op amps is in table vi. aduc832 dac0 dac1 figure 25. buffering the dac outputs the dac output buffer also features a high impedance disable function. in the chip ? s default power-on state, both dacs are disabled, and their outputs are in a high impedance state (or ? three-state ? ) where they remain inactive until enabled in software. this means that if a zero output is desired during power-up or power-down transient conditions, then a pull-down resistor must be added to each dac output. assuming this resistor is in place, the dac outputs will remain at ground potential whenever the dac is disabled. rev. 0 aduc832 ?5 on-chip pll the aduc832 is intended for use with a 32.768 khz watch crystal. a pll locks onto a multiple (512) of this to provide a stable 16.78 mhz clock for the system. the core can operate at this frequency or at binary submultiples of it to allow power saving in cases where maximum core performance is not required. the default core clock is the pll clock divided by 8 or 2.097152 mhz. the adc clocks are also derived from the table x. pllcon sfr bit designations bit name description 7 osc_pd oscillator power-down bit. set by user to halt the 32 khz oscillator in power-down mode. cleared by user to enable the 32 khz oscillator in power-down mode. this feature allows the tic to continue counting even in power-down mode. 6 lock pll lock bit. this is a read only bit. set automatically at power-on to indicate the pll loop is correctly tracking the crystal clock. if the external crystal becomes subsequently disconnected, the pll will rail and the core will halt. cleared automatically at power-on to indicate the pll is not correctly tracking the crystal clock. this may be due to the absence of a crystal clock or an external crystal at power-on. in this mode, the pll output can be 16.78 mhz 20%. 5 ---- reserved for future use; should be written with ?. 4 ---- reserved for future use; should be written with ?. 3 fint fast interrupt response bit set by user enabling the response to any interrupt to be executed at the fastest core clock frequency, regardless of the configuration of the cd2? bits (see below). once user code has returned from an interrupt, the core resumes code execution at the core clock selected by the cd2? bits. cleared by user to disable the fast interrupt response feature. 2 cd2 cpu (core clock) divider bits. 1 cd1 this number determines the frequency at which the microcontroller core will operate. 0 cd0 cd2 cd1 cd0 core clock frequency (mhz) 00 0 16.777216 00 1 8.388608 01 0 4.194304 01 1 2.097152 (default core clock frequency) 10 0 1.048576 10 1 0.524288 11 0 0.262144 11 1 0.131072 pll clock, with the modulator rate being the same as the crys- tal oscillator frequency. the above choice of frequencies ensures that the modulators and the core will be synchronous, regardless of the core clock rate. the pll control register is pllcon. pllcon pll control register sfr address d7h power-on default value 53h bit addressable no rev. 0 e36e aduc832 pulsewidth modulator (pwm) the pwm on the aduc832 is a highly flexible pwm offering programmable resolution and an input clock, and can be config- ured for any one of six different modes of operation. two of these modes allow the pwm to be configured as a - dac with up to 16 bits of resolution. a block diagram of the pwm is shown in figure 26. clock select programmable divider compare mode pwm0h/l pwm1h/l f vco to/external pwm clock f xtal /15 f xtal p2.6 p2.7 16-bit pwm counter figure 26. pwm block diagram the pwm uses five sfrs: the control sfr (pwmcon) and four data sfrs (pwm0h, pwm0l, pwm1h, and pwm1l). pwmcon (as described below) controls the different modes of operation of the pwm as well as the pwm clock frequency. pwm0h/l and pwm1h/l are the data registers that deter- mine the duty cycles of the pwm outputs. the output pins that the pwm uses are determined by the cfg832 register, and can be either p2.6 and p2.7 or p3.4 and p3.3. in this section of the data sheet, it is assumed that p2.6 and p2.7 are selected as the pwm outputs. to use the pwm user software, first write to pwmcon to select the pwm mode of operation and the pwm input clock. writing to pwmcon also resets the pwm counter. in any of the 16-bit modes of operation (modes 1, 3, 4, 6), user software should write to the pwm0l or pwm1l sfrs first. this value is written to a hidden sfr. writing to the pwm0h or pwm1h sfrs updates both the pwmxh and the pwmxl sfrs but does not change the outputs until the end of the pwm cycle in progress. the values written to these 16-bit registers are then used in the next pwm cycle. pwmcon pwm control sfr sfr address aeh power-on default value 00h bit addressable no table xi. pwmcon sfr bit designations bit name description 7 sngl turns off pwm output at p2.6 or p3.4 leaving port pin free for digital i/o. 6 md2 pwm mode bits 5 md1 the md2/1/0 bits choose the pwm mode as follows: 4 md0 md2 md1 md0 mode 000m ode 0: pwm disabled 001m ode 1: single variable resolution pwm on p2.7 or p3.3 010m ode 2: twin 8-bit pwm 011m ode 3: twin 16-bit pwm 100m ode 4: dual nrz 16-bit - dac 101m ode 5: dual 8-bit pwm 110m ode 6: dual rz 16-bit - dac 111r eserved for future use 3c div1 pwm clock divider 2c div0 scale the clock source for the pwm counter as shown below: cdiv1 cdiv0 description 00 pwm counter = selected clock /1 01 pwm counter = selected clock /4 10 pwm counter = selected clock /16 11 pwm counter = selected clock /64 1 csel1 pwm clock divider 0 csel0 select the clock source for the pwm as shown below: csel1 csel0 description 00 pwm clock = f xtal /15 01 pwm clock = f xtal 10 pwm clock = external input at p3.4/t0 11 pwm clock = f vco = 16.777216 mhz rev. 0 aduc832 e37e pwm modes of operation mode 0: pwm disabled the pwm is disabled allowing p2.6 and p2.7 to be used as normal. mode 1: single variable resolution pwm in mode 1, both the pulse length and the cycle time (period) are programmable in user code, allowing the resolution of the pwm to be variable. pwm1h/l sets the period of the output waveform. reducing pwm1h/l reduces the resolution of the pwm output but increases the maximum output rate of the pwm. (e.g., setting pwm1h/l to 65536 gives a 16-bit pwm with a maximum output rate of 266 hz (16.777mhz/65536). setting pwm1h/l to 4096 gives a 12-bit pwm with a maximum output rate of 4096 hz (16.777mhz/4096)). pwm0h/l sets the duty cycle of the pwm output waveform, as shown in figure 27. p2.7 pwm counter pwm1h/l 0 pwm0h/l figure 27. aduc832 pwm in mode 1 mode 2: twin 8-bit pwm in mode 2, the duty cycle of the pwm outputs and the resolution of the pwm outputs are both programmable. the maximum resolution of the pwm output is eight bits. pwm1l sets the period for both pwm outputs. typically, this will be set to 255 (ffh) to give an 8-bit pwm although it is pos- sible to reduce this as necessary. a value of 100 could be loaded here to give a percentage pwm (i.e., the pwm is accurate to 1%). the outputs of the pwm at p2.6 and p2.7 are shown in figure 28. as can be seen, the output of pwm0 (p2.6) goes low when the pwm counter equals pwm0l. the output of pwm1 (p2.7) goes high when the pwm counter equals pwm1h and goes low again when the pwm counter equals pwm0h. setting pwm1h to 0 ensures that both pwm outputs start simultaneously. p2.7 p2.6 pwm counter pwm1h 0 pwm1l pwm0h pwm0l figure 28. pwm mode 2 mode 3: twin 16-bit pwm in mode 3, the pwm counter is fixed to count from 0 to 65536, giving a fixed 16-bit pwm. operating from the 16.777 mhz core clock results in a pwm output rate of 256 hz. the duty cycle of the pwm outputs at p2.6 and p2.7 is independently programmable. as shown in figure 29, while the pwm counter is less than pwm0h/l, the output of pwm0 (p2.6) is high. once the pwm counter equals pwm0h/l, pwm0 (p2.6) goes low and remains low until the pwm counter rolls over. similarly, while the pwm counter is less than pwm1h/l, the output of pwm1 (p2.7) is high. once the pwm counter equals pwm1h/l, pwm1 (p2.7) goes low and remains low until the pwm counter rolls over. in this mode, both pwm outputs are synchronized, i.e., once the pwm counter rolls over to 0, both pwm0 (p2.6) and pwm1 (p2.7) will go high. p2.7 p2.6 pwm counter pwm1h/l 0 65536 pwm0h/l figure 29. pwm mode 3 rev. 0 e38e aduc832 mode 4: dual nrz 16-bit - dac mode 4 provides a high speed pwm output similar to that of a - dac. typically, this mode will be used with the pwm clock equal to 16.777216 mhz. in this mode p2.6 and p2.7 are updated every pwm clock (60 ns in the case of 16 mhz). over any 65536 cycles (16-bit pwm) pwm0 (p2.6) is high for pwm0h/l cycles and low for (65536 ? pwm0h/l) cycles. similarly pwm1 (p2.7) is high for pwm1h/l cycles and low for (65536 ? pwm1h/l) cycles. for example, if pwm1h was set to 4010h (slightly above one quarter of fs) then typically p2.7 will be low for three clocks and high for one clock (each clock is approximately 60 ns). over every 65536 clocks, the pwm will compensate for the fact that the output should be slightly above one quarter of full scale by having a high cycle followed by only two low cycles. 16.777mhz 16-bit 60 s 60 s 0 16-bit 16-bit 16-bit 16-bit 16-bit carry out at p1.0 carry out at p2.7 pwm0h/l = c000h pwm1h/l = 4000h 00 1 000 latch 0 111 11 0 figure 30. pwm mode 4 for faster dac outputs (at lower resolution) write 0s to the lsbs that are not required. if for example only 12 bit perfor- mance is required then write 0s to the four lsbs. this means that a 12-bit accurate s-d dac output can occur at 4.096 khz. similarly writing 0s to the eight lsbs gives an 8-bit accurate s-d dac output at 65 khz. mode 5: dual 8-bit pwm in mode 5, the duty cycle of the pwm outputs and the resolution of the pwm outputs are individually programmable. the maxi- mum resolution of the pwm output is eight bits. the output resolution is set by the pwm1l and pwm1h sfrs for the p2.6 and p2.7 outputs, respectively. pwm0l and pwm0h sets the duty cycles of the pwm outputs at p2.6 and p2.7, respectively. both pwms have same clock source and clock divider. p2.7 p2.6 pwm counters pwm1h 0 pwm1l pwm0h pwm0l figure 31. pwm mode 5 mode 6: dual rz 16-bit - dac mode 6 provides a high speed pwm output similar to that of a - dac. mode 6 operates very similarly to mode 4. however, the key difference is that mode 6 provides return-to-zero (rz) - dac output. mode 4 provides non-return-to-zero - dac outputs. the rz mode ensures that any difference in the rise and fall times will not effect the - dac inl. however, the rz mode halves the dynamic range of the - dac outputs from 0 ? av dd down to 0 ? av dd /2. for best results, this mode should be used with a pwm clock divider of four. if pwm1h was set to 4010h (slightly above one quarter of fs) then typically p2.7 will be low for three full clocks (3 60 ns), high for half a clock (30 ns), and then low again for half a clock (30 ns) before repeating itself. over every 65536 clocks the pwm will compensate for the fact that the output should be slightly above one quarter of full scale by leaving the output high for two half clocks in four every so often. 4mhz 16-bit 240 s 0 16-bit 16-bit 16-bit 16-bit 16-bit carry out at p2.6 carry out at p2.7 pwm0h/l = c000h pwm1h/l = 4000h 00 1 000 latch 0 111 11 0 240 s 0, 3/4, 1/2, 1/4, 0 figure 32. pwm mode 6 rev. 0 aduc832 e39e serial peripheral interface the aduc832 integrates a complete hardware serial peripheral interface (spi) on-chip. spi is an industry standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. it should be noted that the spi pins are shared with the i 2 c pins. therefore, the user can only enable one or the other interface at any given time (see spe in table xii). the spi port can be configured for master or slave operation and typically consists of four pins, namely: miso (master in, slave out data i/o pin) the miso (master in slave out) pin is configured as an input line in master mode and an output line in slave mode. the miso line on the master (data in) should be connected to the miso line in the slave device (data out). the data is transferred as byte wide (8-bit) serial data, msb first. mosi (master out, slave in pin) the mosi (master out slave in) pin is configured as an output line in master mode and an input line in slave mode. the mosi line on the master (data out) should be connected to the mosi line in the slave device (data in). the data is transferred as byte wide (8-bit) serial data, msb first. sclock (serial clock i/o pin) the master serial clock (sclock) is used to synchronize the data being transmitted and received through the mosi and miso data lines. a single data bit is transmitted and received in each sclock period. therefore, a byte is transmitted/received after eight sclock periods. the sclock pin is configured as an output in master mode and as an input in slave mode. in master mode the bit-rate, polarity, and phase of the clock are controlled by the cpol, cpha, spr0, and spr1 bits in the spicon sfr (see table xii). in slave mode the spicon register will have to be configured with the phase and polarity (cpha and cpol) of the expected input clock. in both master and slave modes the data is transmitted on one edge of the sclock signal and sampled on the other. it is important therefore that the cpha and cpol are configured the same for the master and slave devices. ss ss ss ss ss s ss ss s ss sss ss s s s ss s s ss ss sss s s ss s sss ss ss s ss s s ss s s ss s s s s s s s s s sss ss s rev. 0 C40C aduc832 using the spi interface depending on the configuration of the bits in the spicon sfr shown in table xiii, the aduc832 spi interface will transmit or receive data in a number of possible modes. figure 33 shows all possible aduc832 spi configurations and the timing rela- tionships and synchronization between the signals involved. also shown in this figure is the spi interrupt bit (ispi) and how it is triggered at the end of each byte-wide communication. sclock (cp ol = 1) sclock (cp ol = 0) (cpha = 1) (cpha = 0) sample input ispi flag data output ispi flag sample input data output ? msb bit 6 bit 5 ? bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb ss figure 33. spi timing, all modes spi interface?aster mode in master mode, the sclock pin is always an output and gener- ates a burst of eight clocks whenever user code writes to the spidat register. the s clock bit rate is determined by spr 0 and spr1 in spicon. it should also be noted that the ss pin is not used in master mode. if the aduc832 needs to assert the ss pin on an external slave device, a port digital output pin should be used. in master mode, a byte transmission or reception is initiated by a write to spidat. eight clock periods are generated via the sclock pin and the spidat byte being transmitted via mosi. with each sclock period a data bit is also sampled via miso. after eight clocks, the transmitted byte will have been com pletely transmitted and the input byte will be waiting in the input shift register. the ispi flag will be set automatically and an interrupt will occur if enabled. the value in the shift register will be latched into spidat. spi interface?lave mode in slave mode the sclock is an input. the ss pin must also be driven low externally during the byte communication. transmission is also initiated by a write to spidat. in slave mode, a data bit is transmitted via miso and a data bit is re ceived via mosi through each input sclock period. after eight clocks, the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register. the ispi flag will be set automatically and an interrupt will occur if enabled. the value in the shift register will be latched into spidat only when the transmission/reception of a byte has been completed. the end of transmission occurs after the eighth clock has been received if cpha = 1, or when ss returns high if cpha = 0. spidat spi data register function the spidat sfr is written by the user to transmit data over the spi interface or read by user code to read data just received by the spi interface. sfr address f7h power-on default value 00h bit addressable no rev. 0 aduc832 e41e i 2 c compatible interface the aduc832 supports a fully licensed * i 2 c serial interface. the i 2 c interface is implemented as a full hardware slave and software master. sdata is the data i/o pin and sclock is the serial clock. these two pins are shared with the mosi and sclock pins of the on-chip spi interface. therefore, the user can only enable one or the other interface at any given time (see spe in spicon previously). application note uc001 describes the operation of this interface as implemented is available from the microconverter website at www.analog.com/microconverter. three sfrs are used to control the i 2 c interface. these are described below: i2ccon i 2 c control register sfr address e8h power-on default value 00h bit addressable yes table xiii. i2ccon sfr bit designations bit name description 7 mdo i 2 c software master data output bit (master mode only). this data bit is used to implement a master i 2 c transmitter interface in software. data written to this bit will be output on the sdata pin if the data output enable (mde) bit is set. 6 mde i 2 c software master data output enable bit (master mode only). set by user to enable the sdata pin as an output (tx). cleared by the user to enable sdata pin as an input (rx). 5 mco i 2 c software master clock output bit (master mode only). this data bit is used to implement a master i 2 c transmitter interface in software. data written to this bit will be output on the sclock pin. 4 mdi i 2 c software master data input bit (master mode only). this data bit is used to implement a master i 2 c receiver interface in software. data on the s data pin is latched into this bit on sclock if the data output enable (mde) bit is ? 0. ? 3 i2cm i 2 c master/slave mode bit set by user to enable i 2 c software master mode. cleared by user to enable i 2 c hardware slave mode. 2 i2crs i 2 c reset bit (slave mode only). set by user to reset the i 2 c interface. cleared by user code for normal i 2 c operation. 1i 2ctx i 2 c direction transfer bit (slave mode only). set by the microconverter if the interface is transmitting. cleared by the microconverter if the interface is receiving. 0 i2ci i 2 c interrupt bit (slave mode only). set by the microconverter after a byte has been transmitted or received. cleared automatically when user code reads the i2cdat sfr (see i2cdat below). i2cadd i 2 c address register function holds the i 2 c peripheral address for the part. it may be overwritten by user code. technical note uc001 at www.analog.com/microconverter describes the format of the i 2 c standard 7-bit address in detail. sfr address 9bh power-on default value 55h bit addressable no i2cdat i 2 c data register function the i2cdat sfr is written by the user to transmit data over the i 2 c interface or read by user code to read d ata just received by the i 2 c inter face. accessing i2cdat automatically clears any pending i 2 c i nter rupt and the i2ci bit in the i2ccon sfr. user software should only access i2cdat once per interrupt cycle. sfr address 9ah power-on default value 00h bit addressable no * purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use the aduc832 in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. rev. 0 e42e aduc832 the main features of the microconverter i 2 c interface are: ? () () ? , ( ) ? , , , , , , , , , , , ; enabling i2c interrupts for the aduc832 mov ieip2,#01h ; enable i2c interrupt setb ea on the aduc832 an autoclear of the i2ci bit is implemented so this bit is cleared automatically on a read or write access to the i2cdat sfr. mov i2cdat, a ; i2ci autocleared mov a, i2cdat ; i2ci autocleared if for any reason the user tries to clear the interrupt more than once i.e., access the data sfr more than once per interrupt then the i 2 c controller will halt. the interface will then have to be reset using the i2crs bit. the user can choose to poll the i2ci bit or enable the interrupt. in the case of the interrupt, the pc counter will vector to 003bh at the end of each complete byte. for the first byte when the user gets to the i2ci isr, the 7-bit address and the r/ w bit will appear in the i2cdat sfr. the i2ctx bit contains the r/ w bit sent from the master. if i2ctx is set then the master would like to receive a byte. thus the slave will transmit data by writing to the i2cdat register. if i2ctx is cleared the master would like to transmit a byte. therefore, the slave will receive a serial byte. software can interrogate the state of i2ctx to determine whether it should write to or read from i2cdat. once the aduc832 has received a valid address, hardware will hold sclock low until the i2ci bit is cleared by software. this allows the master to wait for the slave to be ready before transmitting the clocks for the next byte. the i2ci interrupt bit will be set every time a complete data byte is received or transmitted, provided it is followed by a valid ack. if the byte is followed by a nack an interrupt is not generated. the aduc832 will continue to issue interrupts for each complete data byte transferred until a stop condition is received or the interface is reset. when a stop condition is received, the interface will reset to a state where it is waiting to be addressed (idle). similarly, if the interface receives a nack at the end of a sequence it also returns to the default idle state. the i2crs bit can be used to reset the i 2 c interface. this bit can be used to force the interface back to the default idle state. it should be noted that there is no way (in hardware) to distinguish between an interrupt generated by a received start + valid address and an interrupt generated by a received data byte. user software must be used to distinguish between these interrupts. rev. 0 aduc832 e43e dual data pointer the aduc832 incorporates two data pointers. the second data pointer is a shadow data pointer and is selected via the data pointer control sfr (dpcon). dpcon also includes some nice features such as automatic hardware post-increment and post-decrement as well as automatic data pointer toggle. dpcon is described in table xiv. dpcon data pointer control sfr sfr address a7h power-on default value 00h bit addressable no table xiv. dpcon sfr bit designations bit name description 7 ---- reserved for future use. 6 dpt data pointer automatic toggle enable. cleared by user to disable auto swapping of the dptr. set in user software to enable automatic toggling of the dptr after each each movx or movc instruction. 5d p1m1 shadow data pointer mode. 4d p1m0 these two bits enable extra modes of the shadow data pointer operation, allowing for more compact and more efficient code size and execution. m1 m0 behavior of the shadow data pointer 00 8052 behavior 01 dptr is post-incremented after a movx or a movc instruction. 10 dptr is post-decremented after a movx or movc instruction. 11 dptr lsb is toggled after a movx or movc instruction. (this instruction can be useful for moving 8-bit blocks to/from 16-bit devices.) 3d p0m1 main data pointer mode. 2d p0m0 these two bits enable extra modes of the main data pointer operation, allowing for more compact and more efficient code size and execution. m1 m0 behavior of the main data pointer 00 8052 behavior 01 dptr is post-incremented after a movx or a movc instruction. 10 dptr is post-decremented after a movx or movc instruction. 11 dptr lsb is toggled after a movx or movc instruction. (this instruction can be useful for moving 8-bit blocks to/from 16-bit devices.) 1 ---- this bit is not implemented to allow the inc dpcon instruction toggle the data pointer without incrementing the rest of the sfr. 0 dpsel data pointer select. cleared by user to select the main data pointer. this means that the contents of this 24-bit register are placed into the three sfrs dpl, dph, and dpp. set by the user to select the shadow data pointer. this means that the contents of a separate 24-bit register appears in the three sfrs dpl, dph, and dpp. note 1: this is the only place where the main and shadow data pointers are distinguished. everywhere else in this data sheet wherever the dptr is mentioned, operation on the active dptr is implied. note 2: only movc/movx @dptr instructions are relevant above. movc/movx pc/@ri instructions will not cause the dptr to automatically post increment/decrement, and so on. to illustrate the operation of dpcon, the following code will copy 256 bytes of code memory at address d000h into xram starting from address 0000h. the following code uses 16 bytes and 2054 cycles. to perform this on a standard 8051 requires approximately 33 bytes and 7172 cycles (depending on how it is implemented). mov dptr,#0 ; main dptr = 0 mov dpcon,#55h ; select shadow dptr ; dptr1 increment mode, ; dptr0 increment mode ; dptr auto toggling on mov dptr,#0d000h ; shadow dptr = d000h moveloop: clr a movc a,@a+dptr ; get data ; post inc dptr ; swap to main dptr (data) movx @dptr,a ; put acc in xram ; increment main dptr ; swap shadow dptr (code) mov a, dpl jnz moveloop rev. 0 e44e aduc832 power supply monitor as its name suggests, the power supply monitor, once enabled, monitors the dv dd supply on the aduc832. it will indicate when any of the supply pins drop below one of four user-selectable voltage trip points from 2.63 v to 4.37 v. for correct operation of the power supply monitor function, av dd must be equal to or greater than 2.7 v. monitor function is controlled via the psmcon sfr. if enabled via the ieip2 sfr, the monitor will interrupt the core using the psmi bit in the psmcon sfr. this bit will not be cleared until the failing power supply has returned above the trip point for at least 250 ms. this monitor function allows the user to save working registers to avoid pos- sible data loss due to the low supply condition, and also ensures that normal code execution will not resume until a safe supply level has been well established. the supply monitor is also pro- tected against spurious glitches triggering the interrupt circuit. psmcon power supply monitor control register sfr address dfh power-on default value deh bit addressable no table xv. psmcon sfr bit designations bit name description 7 ---- reserved. 6 cmpd dv dd comparator bit. this is a read-only bit and directly reflects the state of the dv dd comparator. read ? 1 ? indicates the dv dd supply is above its selected trip point. read ? 0 ? indicates the dv dd supply is below its selected trip point. 5 psmi power supply monitor interrupt bit. this bit will be set high by the microconverter if either cmpa or cmpd is low, indicating low analog or digital supply. the psmi bit can be used to interrupt the processor. once cmpd and/or cmpa return (and remain) high, a 250 ms counter is started. when this counter times out, the psmi interrupt is cleared. psmi can also be written by the user. however, if either com parator output is low, it is not possible for the user to clear psmi. 4 tpd1 dv dd trip point selection bits. 3 tpd0 these bits select the dv dd trip point voltage as follows: tpd1 tpd0 selected dv dd trip point (v) 004. 37 013. 08 102. 93 112. 63 2 ---- reserved 1 ---- reserved 0 psmen power supply monitor enable bit. set to ? 1 ? by the user to enable the power supply monitor circuit. cleared to ? 0 ? by the user to disable the power supply monitor circuit. rev. 0 aduc832 e45e wdcon watchdog timer control register sfr address c0h power-on default value 10h bit addressable yes table xvi. wdcon sfr bit designations bit name description 7 pre3 watchdog timer prescale bits. 6 pre2 the watchdog timeout period is given by the equation: t wd = (2 pre (2 9 /f xtal )) 5 pre1 (0 = ) () , , , , , cleared under the following conditions: user writes ? 0, ? watchdog reset (wdir = ? 0 ? ); hardware reset; psm interrupt. 0 wdwr watchdog write enable bit. to write data into the wdcon sfr involves a double instruction sequence. the wdwr bit must be set and the very next instruction must be a write instruction to the wdcon sfr. for example: clr ea ; disable interrupts while writing ;to wdt setb wdwr ;allow write to wdcon mov wdcon, #72h ;enable wdt for 2.0s timeout setb ea ;enable interrupts again (if rqd) watchdog timer the purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the aduc832 enters an erroneous state, possibly due to a programming error or electrical noise. the watchdog function can be disabled by clearing the wde (watchdog enable) bit in the watchdog control (wdcon) sfr. when enabled, the watchdog circuit will gener- ate a system reset or interrupt (wds) if the user program fails to set the watchdog (wde) bit within a predetermined amount of time (see pre3 ? 0 bits in wdcon). the watchdog timer itself is a 16-bit counter that is clocked directly from the 32.768 khz external crystal. the watchdog time out interval can be adjusted via the pre3 ? 0 bits in wdcon. full control and status of the watchdog timer function can be controlled via the watchdog timer control sfr (wdcon). the wdcon sfr can only be written by user software if the double write sequence described in wdwr below is initiated on every write access to the wdcon sfr. rev. 0 e46e aduc832 time interval counter (tic) a time interval counter is provided on-chip for counting longer intervals than the standard 8051 compatible timers are capable of. the tic is capable of timeout intervals ranging from 1/128 second to 255 hours. furthermore, this counter is clocked by the external 32.768 khz crystal rather than the core clock and has the ability to remain active in power-down mode and time long power-down intervals. this has obvious applications for remote battery-powered sensors where regular widely spaced readings are required. note: instructions to the tic sfrs are also clocked at 32.768 khz, sufficient time must be allowed for in user code for these instructions to execute. six sfrs are associated with the time interval counter, timecon being its control register. depending on the configuration of the it0 and it1 bits in timecon, the selected time counter register overflow will clock the interval counter. when this counter is equal to the time interval value loaded in the i ntval sfr, the tii bit (timecon.2) is set and generates an interrupt if enabled. if the aduc832 is in power-down mode, again with tic interrupt enabled, the tii bit will wake up the device and resume code execution by vectoring directly to the tic interrupt service vector address at 0053h. the tic -related sfrs are described below. note also that the timebase sfrs can be written initially with the current time; the tic can then be controlled and accessed by user software. in effect, this facilitates the im plementation of a real-time clock. a block diagram of the tic is shown in figure 35. timecon tic control register sfr address a1h power-on default value 00h bit addressable no 8-bit prescaler hundredths counter hthsec second counter sec minute counter min hour counter hour tien interval timeout time interval counter interrupt 8-bit interval counter timer intval intval interval timebase selection mux tcen 32.768khz external crystal its0, 1 compare count = intval figure 35. tic, simplified block diagram table xvii. timecon sfr bit designations bit name description 7 ---- reserved for future use. 6 tfh twenty-four hour select bit. set by the user to enable the hour counter to count from 0 to 23. cleared by the user to enable the hour counter to count from 0 to 255. 5 its1 interval timebase selection bits. 4 its0 written by user to determine the interval counter update rate. its1 its0 interval timebase 00 1/128 second 01 seconds 10 minutes 11 hours 3 sti single time interval bit. set by the user to generate a single interval timeout. if set, a timeout will clear the tien bit. cleared by the user to allow the interval counter to be automatically reloaded and start counting again at each interval timeout. 2 tii tic interrupt bit. set when the 8-bit interval counter matches the value in the intval sfr. cleared by user software. 1 tien time interval enable bit. set by the user to enable the 8-bit time interval counter. cleared by the user to disable the interval counter. 0 tcen time clock enable bit. set by the user to enable the time clock to the time interval counters. cleared by the user to disable the clock to the time interval counters and reset the time interval sfrs to the last value written to them by the user. the time registers (hthsec, sec, min, and hour) can be written while tcen is low. rev. 0 aduc832 e47e intval user time interval select register function user code writes the required time interval to this register. when the 8-bit interval counter is equal to the time interval value loaded in the intval sfr, the tii bit (timecon.2) is set and generates an interrupt if enabled. sfr address a6h power-on default value 00h bit addressable no valid value 0 to 255 decimal hthsec hundredths seconds time register function this register is incremented in 1/128 second intervals once tcen in timecon is active. the hthsec sfr counts from 0 to 127 before rolling over to increment the sec time register. sfr address a2h power-on default value 00h bit addressable no valid value 0 to 127 decimal sec seconds time register function this register is incremented in 1-second intervals once tcen in timecon is active. the sec sfr counts from 0 to 59 before rolling over to increment the min time register. sfr address a3h power-on default value 00h bit addressable no valid value 0 to 59 decimal min minutes time register function this register is incremented in 1-minute intervals once tcen in timecon is active. the min counts from 0 to 59 before rolling over to increment the hour time register sfr address a4h power-on default value 00h bit addressable no valid value 0 to 59 decimal hour hours time register function this register is incremented in 1-hour intervals once tcen in timecon is active. the hour sfr counts from 0 to 23 before rolling over to 0. sfr address a5h power-on default value 00h bit addressable no valid value 0 to 23 decimal rev. 0 e48e aduc832 8052 compatible on-chip peripherals this section gives a brief overview of the various secondary peripheral circuits that are also available to the user on-chip. these remaining functions are mostly 8052 compatible (with a few additional features) and are controlled via standard 8052 sfr bit definitions. parallel i/o the aduc832 uses four input/output ports to exchange data with external devices. in addition to performing general-purpose i/o, some ports are capable of external memory operations while others are multiplexed with alternate functions for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general-purpose i/o pin. port 0 port 0 is an 8-bit open drain bidirectional i/o port that is directly controlled via the port 0 sfr. port 0 is also the multi- plexed low order address and data bus during accesses to external program or data memory. figure 36 shows a typical bit latch and i/o buffer for a port 0 port pin. the bit latch (one bit in the port ? s sfr) is represented as a type d flip-flop, which will clock in a value from the internal bus in response to a ? write to latch ? signal from the cpu. the q output of the flip-flop is placed on the internal bus in response to a ? read latch ? signal from the cpu. the level of the port pin itself is placed on the internal bus in response to a ? read pin ? signal from the cpu. some instructions that read a port activate the ? read latch ? signal, and others activate the ? read pin ? signal. see the following read-modify-write instructions section for more details. control read latch internal bus write to latch read pin d cl q q atc dv dd addr/data p0 pin p0i/o ap0 addraddr/data contro dp0sr1 1w contro addr/datat p0 ii/op01 p0sr ip0 t nandcontro ete p0 p00 v o 1a p1 p1p1sr p1 p1 1 p1t 0 t tviii tviii p1ap p a p10 tt/cei p11 tet/cc/rt p1 ss ssspii read atc interna s write toatc read pin d c q q atc p1 pin toadc p1i/o p p psrp ap addraddr/data contro p0icontro1 addrp0sr psr rev. 0 aduc832 e49e in general-purpose i/o port mode, port 2 pins that have 1s written to them are pulled high by the internal pull-ups (figure 39) and, in that state, can be used as inputs. as inputs, port 2 pins being pulled externally low will source current because of the internal pull-up resistors. port 2 pins with 0s written to them will drive a logic low output voltage (v ol ) and will be capable of sinking 1.6 ma. p2.6 and p2.7 can also be used as pwm outputs. in the case that they are selected as the pwm outputs via the cfg832 sfr, the pwm outputs will overwrite anything written to p2.6 or p2.7. control read latch internal bus write to latch read pin d cl q q atc dv dd addr p pin dv dd interna pp seeireor detaisointernapp pi/o q ro port atc c dea q1 dv dd q dv dd q dv dd p pin q ipc p p psrp1 ap p0 v o a p titp psr1 o0 ti pap p a p0 rdartipsdi/o0 p1 tdartop sco0 p int0 ei0 p int1 ei1/pw1/iso p t0t/c0ei pwec/pw0 p t1t/c1ei p wr edws p rd edrs pppwi pwcsr pwpp read atc interna s write toatc read pin d c q q atc dv dd p pin interna pp seeire ordetaiso internapp aternate otpt nction aternate inpt nction 0pi/o adi/o ispi/i cscoc sdata/osi ti/o 1 spi i c ni cspe0et q1q spispe1et q1spi ii cspe0etqq 00 ispispe1 etq p0 p oscocs spi scocsdatai c 0 nscocsdata/osi sri c tspii c ardwarespi aster/save q scitt trier q1 qo dv dd scoc pin qo spe1spienae 1 scocpi/oe spi rev. 0 e50e aduc832 mco i2cm sfr bits 50ns glitch rejection filter hardware i 2 c (slave only) q3 q4 sclock pin q2 q1 (off) dv dd spe = 0 (i 2 c e nable) figure 42. sclock pin i/o functional equivalent in i 2 c mode hardware spi (master/slave) q3 q1 q2 (off) dv dd sdata/ mosi pin q4 (off) spe = 1 (spi enable) figure 43. sdata/mosi pin i/o functional equivalent in spi mode q3 q4 q2 q1 (off) dv dd mdi mdo mde i2cm hardware i 2 c (slave only) 50ns glitch rejection filter sdata/ mosi pin sfr bits spe = 0 (i 2 c e nable) figure 44. sdata/mosi pin i/o functional equivalent in i 2 c mode miso is shared with p3.3 and as such has the same configuration as that shown in figure 40. read-modify-write instructions some 8051 instructions that read a port read the latch while others read the pin. the instructions that read the latch rather than the pins are the ones that read a value, possibly change it, and then rewrite it to the latch. these are called ? read-modify- write ? instructions. listed below are the read-modify-write instructions. when the destination operand is a port, or a port bit, these instructions read the latch rather than the pin. anl (logical and, e.g., anl p1, a) orl (logical or, e.g., orl p2, a) xrl (logical ex-or, e.g., xrl p3, a) jbc (jump if bit = 1 and clear bit, e.g., jbc p1.1, label) cpl (complement bit, e.g., cpl p3.0) inc (increment, e.g., inc p2) dec (decrement, e.g., dec p2) djnz (decrement and jump if not zero, e.g., djnz p3, label) mov px.y, c * (move carry to bit y of port x) clr px.y * (clear bit y of port x) setb px.y * (set bit y of port x) the reason that read-modify-write instructions are directed to the latch rather than the pin is to avoid a possible misinterpreta- tion of the voltage level of a pin. for example, a port pin might be used to drive the base of a transistor. when a 1 is written to the bit, the transistor is turned on. if the cpu then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transistor and interpret it as a logic 0. reading the latch rather than the pin will return the correct value of 1. * these instructions read the port byte (all 8 bits), modify the addressed bit and then write the new byte back to the latch. rev. 0 aduc832 e51e user configuration and control of all timer operating modes is achieved via three sfrs: tmod, tcon control and configuration for timers 0 and 1. t2con control and configuration for timer 2. tmod timer/counter 0 and 1 mode register sfr address 89h power-on default value 00h bit addressable no table xx. tmod sfr bit designations bit name description 7 gate timer 1 gating control. set by software to enable timer/counter 1 only while int1 pin is high and tr1 control bit is set. cleared by software to enable timer 1 whenever tr1 control bit is set. 6 c/t timer 1 timer or counter select bit. set by software to select counter operation (input from t1 pin). cleared by software to select timer operation (input from internal system clock). 5m 1t imer 1 mode select bit 1 (used with m0 bit). 4m 0t imer 1 mode select bit 0. m1 m0 00 th1 operates as an 8-bit timer/counter. tl1 serves as 5-bit pre scaler. 01 16-bit timer/ counter. th1 and tl1 are cascaded; there is no prescaler. 10 8-bit auto-r eload timer/counter. th1 holds a value that is to be re loaded into tl1 each time it overflows. 11 timer/counter 1 stopped. 3 gate timer 0 gating control. set by software to enable timer/counter 0 only while int0 pin is high and tr0 control bit is set. cleared by software to enable timer 0 whenever tr0 control bit is set. 2 c/t timer 0 timer or counter select bit. set by software to select counter operation (input from t0 pin). cleared by software to select timer operation (input from internal system clock). 1m 1t imer 0 mode select bit 1. 0m 0t imer 0 mode select bit 0. m1 m0 00 th0 operates as an 8-bit timer/counter. tl0 serves as a 5-bit prescaler. 01 16-bit timer/counter. th0 and tl0 are cascaded; there is no prescaler. 10 8 -bit auto-reload timer/counter. th0 holds a value that is to be re loaded into tl0 each time it overflows. 11 tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer only, controlled by timer 1 control bits. timers/counters the aduc832 has three 16-bit timer/counters: timer 0, timer 1, and timer 2. the timer/counter hardware has been included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in soft- ware. each timer/counter consists of two 8-bit registers thx and tlx (x = 0, 1 and 2). all three can be configured to operate either as timers or event counters. in timer function, the tlx register is incremented every machine cycle. thus, one can think of it as counting machine cycles. since a machine cycle consists of 12 core clock periods, the maximum count rate is 1/12 the core clock frequency. in counter function, the tlx register is incremented by a 1-to-0 transition at its corresponding external input pin, t0, t1, or t2. in this function, the external input is sampled during s5p2 of every machine cycle. when the samples show a high in one cycle and a low in the next cycle, the count is incremented. the new count value appears in the register during s3p1 of the cycle following the one in which the transition was detected. since it takes two machine cycles (24 core clock periods) to recognize a 1-to-0 transition, the maximum count rate is 1/24 the core clock frequency. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for a minimum of one full machine cycle. rev. 0 e52e aduc832 tcon timer/counter 0 and 1 control register sfr address 88h power-on default value 00h bit addressable yes table xxi. tcon sfr bit designations bit name description 7 tf1 timer 1 overflow flag. set by hardware on a timer/counter 1 overflow. cleared by hardware when the program counter (pc) vectors to the interrupt service routine. 6 tr1 timer 1 run control bit. set by the user to turn on timer/counter 1. cleared by the user to turn off timer/counter 1. 5 tf0 timer 0 overflow flag. set by hardware on a timer/counter 0 overflow. cleared by hardware when the pc vectors to the interrupt service routine. 4 tr0 timer 0 run control bit. set by the user to turn on timer/counter 0. cleared by the user to turn off timer/counter 0. 3 ie1 * external interrupt 1 ( int1 ) flag. set by hardware by a falling edge or zero level being applied to external interrupt pin int1 , depending on bit it1 state. cleared by hardware when the pc vectors to the interrupt service routine only if the interrupt was transition-activated. if level-activated, the external requesting source controls the request flag, rather than the on-chip hardware. 2 it1 * external interrupt 1 (ie1) trigger type. set by software to specify edge-sensitive detection (i.e., 1-to-0 transition). cleared by software to specify level-sensitive detection (i.e., zero level). 1 ie0 * external interrupt 0 ( int0 ) flag. set by hardware by a falling edge or zero level being applied to external interrupt pin i nt0 , depending on bit it0 state. cleared by hardware when the pc vectors to the interrupt service routine only if the interrupt was transition-activated. if level-activated, the external requesting source controls the request flag, rather than the on-chip hardware. 0 it0 * external interrupt 0 (ie0) trigger type. set by software to specify edge-sensitive detection (i.e., 1-to-0 transition). cleared by software to specify level-sensitive detection (i.e., zero level). * these bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the exte rnal int0 and int1 interrupt pins. timer/counter 0 and 1 data registers each timer consists of two 8-bit registers. these can be used as independent registers or combined to be a single 16-bit register depending on the timer mode configuration. th0 and tl0 timer 0 high byte and low byte. sfr address = 8ch, 8ah, respectively. th1 and tl1 timer 1 high byte and low byte. sfr address = 8dh, 8bh, respectively. rev. 0 aduc832 e53e timer/counter 0 and 1 operating modes the following paragraphs describe the operating modes for timer/counters 0 and 1. unless otherwise noted, it should be assumed that these modes of operation are the same for timer 0 as for timer 1. mode 0 (13-bit timer/counter) mode 0 configures an 8-bit timer/counter with a divide-by-32 prescaler. figure 45 shows mode 0 operation. 12 core clk * control p3.4/t0 gate p3.2/ int0 tr0 t0 t0 its t0 its interrpt c/t 0 c/t 1 corecisdeinedtecditsinpcon t/c00 i1 a10 t0tt0 t tr010 int0 1s1 int0 tr0 tcontodt1 t0t0 t t0 s tr0 11t/c 10 11 1 core c contro p/t0 ate p/ int0 tr0 t0 t0 its t0 its interrpt c/t0 c/t1 corecisdeinedtecditsinpcon t/c01 t/ca t0 ot0 t0t0t0 tt0 contro t0 t0 its interrpt reoad t0 its 1 core c p/t0 ate p/into tr0 c/ t0 c/ t1 corecisdeinedtecditsinpcon t/c0 tt/c t0t1t1 t tr10t0t0t0 tt0 t0c/ttr0 int0 t0 t0 tr1t1t1t t0 t1 wt0t1 b aud rate generator . in fact, it can be used in any application not requiring an interrupt from timer 1 itself. control tf0 tl0 (8 bits) interrupt 12 core clk * p3.4/t0 gate p3.2/ int0 tr0 c/t0 c/t1 corecisdeinedtecditsinpcon core c/1 t1 t0 its interrpt core c/1 tr1 t/c0 rev. 0 e54e aduc832 t2con timer/counter 2 control register sfr address c8h power-on default value 00h bit addressable yes table xxii. t2con sfr bit designations bit name description 7 tf2 timer 2 overflow flag. set by hardware on a timer 2 overflow. tf2 will not be set when either rclk = 1 or tclk = 1. cleared by user software. 6 exf2 timer 2 external flag. set by hardware when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. cleared by user software. 5 rclk receive clock enable bit. set by the user to enable the serial port to use timer 2 overflow pulses for its receive clock in serial port modes 1 and 3. cleared by the user to enable timer 1 overflow to be used for the receive clock. 4 tclk transmit clock enable bit. set by the user to enable the serial port to use timer 2 overflow pulses for its transmit clock in serial port modes 1 and 3. cleared by the user to enable timer 1 overflow to be used for the transmit clock. 3 exen2 timer 2 external enable flag. set by the user to enable a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. cleared by the user for timer 2 to ignore events at t2ex. 2 tr2 timer 2 start/stop control bit. set by the user to start timer 2. cleared by the user to stop timer 2. 1 cnt2 timer 2 timer or counter function select bit. set by the user to select counter function (input from external t2 pin). cleared by the user to select timer function (input from on-chip core clock). 0 cap2 timer 2 capture/reload select bit. set by the user to enable captures on negative transitions at t2ex if exen2 = 1. cleared by the user to enable autoreloads with timer 2 overflows or negative transitions at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to autoreload on timer 2 overflow. timer/counter 2 data registers timer/counter 2 also has two pairs of 8-bit data registers associated with it. these are used as both timer data registers and timer capture/reload registers. th2 and tl2 timer 2, data high byte and low byte. sfr address = cdh, cch respectively. rcap2h and rcap2l timer 2, capture/reload byte and low byte. sfr address = cbh, cah respectively. rev. 0 aduc832 e55e timer/counter operation modes the following paragraphs describe the operating modes for ti m er/ counter 2. the operating modes are selected by bits in the t2con sfr as shown in table xxiii. table xxiii. t2con operating modes rclk (or) tclk cap2 tr2 mode 00 1 16-bit autoreload 01 1 16-bit capture 1x 1b aud rate xx0 off 16-bit autoreload mode in autoreload mode, there are two options, which are selected by bit exen2 in t2con. if exen2 = 0, then when timer 2 rolls over it not only sets tf2 but also causes the timer 2 regis ters to be reloaded with the 16-bit value in registers rcap2l and rcap2h, which are preset by software. if exen2 = 1, then timer 2 still performs the above, but with the added feature that a 1 -to-0 transition at external input t2ex will also trigger th e 16-bit reload and set exf2. the autoreload mode is illus- trated in figure 49. 16-bit capture mode in the capture mode, there are again two options, which are selected by bit exen2 in t2con. if exen2 = 0, then timer 2 is a 16-bit timer or counter that, upon overflowing, sets bit tf2, the timer 2 overflow bit, which can be used to generate an interrupt. if exen2 = 1, then timer 2 still performs the above, but a l-to-0 transition on external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2, like tf2, can generate an interrupt. the capture mode is illustrated in figure 50. the baud rate generator mode is selected by rclk = 1 and/or tclk = 1. in either case, if timer 2 is being used to generate the baud rate, the tf2 interrupt flag will not occur. therefore, timer 2 interrupts will not occur so they do not have to be disabled. in this mode the exf2 flag, however, can still cause interrupts and this can be used as a third external interrupt. baud rate generation will be described as part of the uart serial port operation in the following pages. core clk * 12 t2 pin c/ t2 = 0 c/t2 = 1 tr2 control tl2 (8 bits) th2 (8 bits) reload tf2 exf2 timer interrupt exen2 control transition detector t2ex pin rcap2l rcap2h * core clk is defined by the cd bits in pllcon figure 49. timer/counter 2, 16-bit autoreload mode tf2 core clk * 12 t2 pin tr2 control tl2 (8 bits) th2 (8 bits) capture exf2 timer interrupt exen2 control transition detector t2ex pin rcap2l rcap2h c/ t2 = 0 c/ t2 = 1 * core clk is defined by the cd bits in pllcon figure 50. timer/counter 2, 16-bit capture mode rev. 0 e56e aduc832 uart serial interface the serial port is full duplex, meaning it can transmit and receive simultaneously. it is also receive-buffered, meaning it can com- mence reception of a second byte before a previously received byte has been read from the receive register. however, if the first byte still has not been read by the time reception of the second byte is complete, the first byte will be lost. the physical interface to the serial data network is via pins rxd(p3.0) and txd(p3.1) while the sfr interface to the uart is comprised of sbuf and scon, as described below. sbuf the serial port receive and transmit registers are both accessed through the sbuf sfr (sfr address = 99h). writing to sbuf loads the transmit register and reading sbuf accesses a physically separate receive register. scon uart serial port control register sfr address 98h power-on default value 00h bit addressable yes table xxiv. scon sfr bit designations bit name description 7 sm0 uart serial mode select bits. 6 sm1 these bits select the serial port operating mode as follows: sm0 sm1 selected operating mode 00 mode 0: shift register, fixed baud rate (core_clk/2) 01 mode 1: 8-bit uart, variable baud rate 10 mode 2: 9-bit uart, fixed baud rate (core_clk/64) or (core_clk/32) 11 mode 3: 9-bit uart, variable baud rate 5 sm2 multiprocessor communication enable bit. enables multiprocessor communication in modes 2 and 3. in mode 0, sm2 should be cleared. in mode 1, if sm2 is set, ri will not be activated if a valid stop bit was not received. if sm2 is cleared, ri will be set as soon as the byte of data has been received. in modes 2 or 3, if sm2 is set, ri will not be activated if the received ninth data bit in rb8 is 0. if sm2 is cleared, ri will be set as soon as the byte of data has been received. 4 ren serial port receive enable bit. set by user software to enable serial port reception. cleared by user software to disable serial port reception. 3t b8 serial port transmit (bit 9). the data loaded into tb8 will be the ninth data bit that will be transmitted in modes 2 and 3. 2 rb8 serial port receiver bit 9. the ninth data bit received in modes 2 and 3 is latched into rb8. for mode 1 the stop bit is latched into rb8. 1t i serial port transmit interrupt flag. set by hardware at the end of the eighth bit in mode 0, or at the beginning of the stop bit in modes 1, 2, and 3. ti must be cleared by user software. 0r i serial port receive interrupt flag. set by h ardware at the end of the eighth bit in mode 0, or halfway through the stop bit in modes 1, 2, and 3. ri must be cleared by software. rev. 0 aduc832 e57e mode 0: 8-bit shift register mode mode 0 is selected by clearing both the sm0 and sm1 bits in the s fr scon. serial data enters and exits through rxd. txd outputs the shift clock. eight data bits are transmitted or received. transmission is initiated by any instruction that writes to sbuf. the data is shifted out of the rxd line. the eight bits are transmitted w ith the least-significant bit (lsb) first, as shown in figure 51. core clk ale rxd (data out) txd (shift clock) data bit 0 data bit 1 data bit 6 data bit 7 s6 s5 s4 s3 s2 s1 s6 s5 s4 s4 s3 s2 s1 s6 s5 s4 s3 s2 s1 machine cycle 8 machine cycle 7 machine cycle 2 machine cycle 1 figure 51. uart serial port transmission, mode 0 reception is initiated when the receive enable bit (ren) is 1 and the receive interrupt bit (ri) is 0. when ri is cleared the data is cl ocked into the rxd line and the clock pulses are output from the txd line. mode 1: 8-bit uart, variable baud rate mode 1 is selected by clearing sm0 and setting sm1. each data byte (lsb first) is preceded by a start bit (0) and followed by a stop bit (1). therefore, 10 bits are transmitted on txd or received on rxd. the baud rate is set by the timer 1 or timer 2 overflow rate, or a combination of the two (one for transmission and the other for reception). transmission is initiated by writing to sbuf. the ? write to sbuf ? signal also loads a 1 (stop bit) into the ninth bit position of the transmit shift register. the data is output bit by bit until the stop bit appears on txd and the transmit interrupt flag (ti) is automatically set as shown in figure 52. txd ti (sco n.1) start bit d0 d1 d2 d3 d4 d5 d6 d7 stop bit set interrupt i.e., re ady for more data figure 52. uart serial port transmission, mode 0 reception is initiated when a 1-to-0 transition is detected on rx d. assuming a valid start bit was detected, character reception continues. the start bit is skipped and the eight data bits are clocked into the serial port shift register. when all eight bits have been clocked in, the following events occur: the eight bits in the receive shift register are latched into sbuf. the ninth bit (stop bit) is clocked into rb8 in scon. the receiver interrupt flag (ri) is set. this will be the case if, and only if, the following conditions are met at the time the final shift pulse is generated: ri = 0, and either sm2 = 0 or sm2 = 1, and the received stop bit = 1. if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. mode 2: 9-bit uart with fixed baud rate mode 2 is selected by setting sm0 and clearing sm1. in this mode, the uart operates in 9-bit mode with a fixed baud rate. the baud rate is fixed at core_clk/64 by default, although by setting the smod bit in pcon, the frequency can be doubled to core_clk/32. eleven bits are transmitted or received, a start bit (0), eight data bits, a programmable ninth bit, and a stop bit (1). the ninth bit is most often used as a parity bit, although it can be used for anything, including a ninth data bit if required. to transmit, the eight data bits must be written into sbuf. the ninth bit must be written to tb8 in scon. when transmission is initiated, the eight data bits (from sbuf) are loaded onto the transmit shift register (lsb first). the contents of tb8 are loaded into the ninth bit position of the transmit shift register. the transmission will start at the next valid baud rate clock. the ti flag is set as soon as the stop bit appears on txd. reception for mode 2 is similar to that of mode 1. the eight data bytes are input at rxd (lsb first) and loaded onto the receive shift register. when all eight bits have been clocked in, the following events occur: the eight bits in the receive shift register are latched into sbuf. the ninth data bit is latched into rb8 in scon. the receiver interrupt flag (ri) is set. this will be the case if, and only if, the following conditions are met at the time the final shift pulse is generated: ri = 0, and either sm2 = 0 or sm2 = 1, and the received stop bit = 1. if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. mode 3: 9-bit uart with variable baud rate mode 3 is selected by setting both sm0 and sm1. in this mode, the 8051 uart serial port operates in 9-bit mode with a vari able baud rate determined by either timer 1 or timer 2. the opera- tion of the 9-bit uart is the same as for mode 2 but the baud rate can be varied as for mode 1. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. uart serial port baud rate generation mode 0 baud rate generation the baud rate in mode 0 is fixed: mode baud rate = (core clock frequency / ) 012 mode 2 baud rate generation the baud rate in mode 2 depends on the value of the smod bit in the pcon sfr. if smod = 0, the baud rate is 1/64 of the core clock. if smod = 1, the baud rate is 1/32 of the core clock: mode baud rate = ( / ) core clock frequency) smod 2264 ( modes 1 and 3 baud rate generation the baud rates in modes 1 and 3 are determined by the overflow rate in timer 1 or timer 2, or both (one for transmit and the other for receive). rev. 0 e58e aduc832 core clk * 2 t2 pin tr2 control tl2 (8 bits) th2 (8 bits) reload exen2 control t2ex pin transition detector exf 2 timer 2 interrupt note availability of additional external interrupt * core clk is defined by the cd bits in pllcon rcap2l rcap2h timer 2 overflow 2 16 16 rclk tclk rx clock tx clock 0 0 1 1 1 0 smod timer 1 overflow c/ t2 = 0 c/ t2 = 1 osc. freq. is divided by 2, not 12. figure 53. timer 2, uart baud rates timer 1 generated baud rates when timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod as follows: modes and baud rate = (/ ) (timer overflow rate) smod 13 232 1 , , ( = ) , modes and baud rate = / core clock / ( ? th smod 13 ()( [ ])) 232 12 256 1 , () , () () () () () , modes and baud rate = ( / ) (timer overflow rate) 13 116 2 , , , , , , modes 1 and 3 baud rate = (core clk)/( ? rcap h, rcap l 32 65536 2 2 ( )) , () () () () () () () () () () () () () () () rev. 0 aduc832 e59e timer 3 generated baud rates the high integer dividers in a uart block mean that high speed baud rates are not always possible using some particular crystals. for example, using a 12 mhz crystal, a baud rate of 115200 is not possible. to address this problem, the aduc832 has added a dedicated baud rate timer (timer 3) specifically for generating highly accurate baud rates. timer 3 can be used instead of timer 1 or timer 2 for generating very accurate high speed uart baud rates including 115200 and 230400. timer 3 also allows a much wider range of baud rates to be obtained. in fact, every desired bit rate from 12 bit/s to 393216 bit/s can be generated to within an error of , (1 + t3fd/64) 2 t3 rx/tx clock core clk * t3en rx clock tx clock timer 1/timer 2 rx clock (fig 53) fractional divider 0 0 1 1 timer 1/timer 2 tx clock (fig 53) 16 2 div * core clk is defined by the cd bits in pllcon figure 54. timer 3, uart baud rates two sfrs (t3con and t3fd) are used to control timer 3. t3con is the baud rate control sfr, allowing timer 3 to be used to set up the uart baud rate, and setting up the binary divider (div). table xxvii. t3con sfr bit designations bit name description 7 t3bauden t3uartbaud enable set to enable timer 3 to generate the baud rate. when set pcon.7, t2con.4 and t2con.5 are ignored. cleared to let the baud rate be generated as per a standard 8052. 6 - 5 - 4 - 3 - 2 div2 binary divider factor 1 div1 div2 div1 div0 bin divider 0 div0 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 the appropriate value to write to the div2-1-0 bits can be calculated using the following formula where f core defined in pllcon sfr: note: the div value must be rounded down. div f core = ? ? ? ? ? ? ( ) baud rate t3fd is the fractional divider ratio required to achieve the required baud rate. we can calculate the appropriate value for t3fd using the following formula: note: t3fd should be rounded to the nearest integer. tfd f baud rate core div 3 2 2 = once the values for div and t3fd are calculated the actual baud rate can be calculated using the following formula: actual baud rate = + f tfd core div () for example, to get a baud rate of 115200 while operating at 16.7 mhz div log log tfd h = () () == = () () == , rev. 0 e60e aduc832 interrupt system the aduc832 provides a total of nine interrupt sources with two priority levels. the control and configuration of the interrupt system is carried out through three interrupt-related sfrs. ie interrupt enable register ip interrupt priority register ieip2 secondary interrupt enable register ie interrupt enable register sfr address a8h power-on default value 00h bit addressable yes table xxix. ie sfr bit designations bit name description 7e aw ritten by user to enable ? 1 ? or disable ? 0 ? all interrupt sources 6 eadc written by user to enable ? 1 ? or disable ? 0 ? adc interrupt 5 et2 written by user to enable ? 1 ? or disable ? 0 ? timer 2 interrupt 4e sw ritten by user to enable ? 1 ? or disable ? 0 ? uart serial port interrupt 3 et1 written by user to enable ? 1 ? or disable ? 0 ? timer 1 interrupt 2 ex1 written by user to enable ? 1 ? or disable ? 0 ? external interrupt 1 1 et0 written by user to enable ? 1 ? or disable ? 0 ? timer 0 interrupt 0 ex0 written by user to enable ? 1 ? or disable ? 0 ? external interrupt 0 ip interrupt priority register sfr address b8h power-on default value 00h bit addressable yes table xxx. ip sfr bit designations bit name description 7 ---- reserved for future use 6 padc written by user to select adc interrupt priority ( ? 1 ? = high; ? 0 ? = low) 5 pt2 written by user to select timer 2 interrupt priority ( ? 1 ? = high; ? 0 ? = low) 4p sw ritten by user to select uart serial port interrupt priority ( ? 1 ? = high; ? 0 ? = low) 3 pt1 written by user to select timer 1 interrupt priority ( ? 1 ? = high; ? 0 ? = low) 2 px1 written by user to select external interrupt 1 priority ( ? 1 ? = high; ? 0 ? = low) 1 pt0 written by user to select timer 0 interrupt priority ( ? 1 ? = high; ? 0 ? = low) 0 px0 written by user to select external interrupt 0 priority ( ? 1 ? = high; ? 0 ? = low) ieip2 secondary interrupt enable register sfr address a9h power-on default value a0h bit addressable no table xxxi. ieip2 sfr bit designations bit name description 7 ---- reserved for future use 6p ti priority for time interval interrupt 5 ppsm priority for power supply monitor interrupt 4 psi priority for spi/i 2 c interrupt 3 ---- this bit must contain zero. 2 eti written by user to enable ? 1 ? or disable ? 0 ? time interval counter interrupt. 1 epsmi written by user to enable ? 1 ? or disable ? 0 ? power supply monitor interrupt. 0 esi written by user to enable ? 1 ? or disable ? 0 ? spi or i 2 c serial port interrupt. rev. 0 aduc832 e61e interrupt priority the interrupt enable registers are written by the user to enable i ndividual interrupt sources, while the interrupt priority registers allow the user to select one of two priority levels for each interrupt. an interrupt of a high priority may interrupt the service routine of a low priority interrupt, and if two interrupts of different priority o ccur at the same time, the higher level interrupt will be serviced first. an interrupt cannot be interrupted by another interrupt of t he same priority level. if two interrupts of the same priority level o ccur simultaneously, a polling sequence is observed as shown in table xxxii. table xxxii. priority within an interrupt level source priority description psmi 1 (highest) power supply monitor interrupt wds 2 watchdog timer interrupt ie0 2 external interrupt 0 adci 3 adc interrupt tf0 4 timer/counter 0 interrupt ie1 5 external interrupt 1 tf1 6 timer/counter 1 interrupt ispi/i2ci 7 spi interrupt/i 2 c interrupt ri + ti 8 serial interrupt tf2 + exf2 9 (lowest) timer/counter 2 interrupt tii 11(lowest) time interval counter interrupt interrupt vectors when an interrupt occurs, the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter. the interrupt vector addresses are shown in table xxxiii. table xxxiii. interrupt vector addresses source vector address ie0 0003h tf0 000bh ie1 0013h tf1 001bh ri + ti 0023h tf2 + exf2 002bh adci 0033h ispi/i2ci 003bh psmi 0043h tii 0053h wds 005bh aduc832 hardware design considerations this section outlines some of the key hardware design consider- ations that must be addressed when integrating the aduc832 into any hardware system. clock oscillator the clock source for the aduc832 can be generated by the internal pll or by an external clock input. to use the internal pll, connect a 32.768 khz parallel resonant crystal between xtal1 and xtal2, and connect a capacitor from each pin to ground as shown below. this crystal allows the pll to lock cor- rectly to give a f vco of 16.777216 mhz. if no crystal is present, the pll will free run, giving a f vco of 16.7 mhz 20%. this is useful if an external clock input is required. the part will power up and the pll will free run; the user then in software writes to the cfg832 sfr to enable the external clock input on p3.4. xtal2 xtal1 to internal timing circuits aduc832 figure 55. external parallel resonant crystal connections p3.4 to internal timing circuits aduc832 external clock source figure 56. connecting an external clock source whether using the internal pll or an external clock source, the aduc832 ? s specified operational clock speed range is 400 khz to 16.777216 mhz. the core itself is static, and will function all the way down to dc. but at clock speeds slower that 400 khz, the adc will no longer function correctly. therefore, to ensure specified operation, use a clock frequency of at least 400 khz and no more than 16.777216 mhz. rev. 0 e62e aduc832 external memory interface in addition to its internal program and data memories, the aduc832 can access up to 64 kbytes of external program memory (rom/prom/and so on.) and up to 16 mbytes of external data memory (sram). to select from which code space (internal or external program memory) to begin executing instructions, tie the ea (external access) pin high or low, respectively. when ea is high (pulled up to v dd ), user program execution will start at address 0 of the internal 62 kbytes flash/ee code space. when ea is low (tied to ground) u ser program execution will start at address 0 of the external code space. a second very important function of the ea pin is described in the single pin emulation mode section. external program memory (if used) must be connected to the aduc832 as illustrated in figure 57. note that 16 i/o lines (ports 0 and 2) are dedicated to bus functions during external program memory fetches. port 0 (p0) serves as a multiplexed address/data bus. it emits the low byte of the program counter (pcl) as an address, and then goes into a float state awaiting the arrival of the code byte from the program memory. during the time that the low byte of the program counter is valid on p0, the sign al ale (address latch enable) clocks this byte into an address latch. meanwhile, port 2 (p2) emits the high byte of the pro gram c ounter (pch), then psen strobes the eprom a nd th e c ode byte is read into the aduc832. latch eprom oe aa1 a0a d0d instrction adc psen p ae p0 epi n1 e p0p w p0/ i/o t / rat 01c atc sra oe aa1 a0a d0d data adc rd p ae p0 we wr edi as ira adc1 ra atc adc rd p ae p0 wr atc sra oe aa1 a0a d0d data we a1a edi1 as ip0p0 /idp ae adc srapp dppae dpipdpp sra01 ps tadc v va v v , , , , , rev. 0 aduc832 ?3 separate analog and digital power supply pins (av dd and dv dd , respectively) allow av dd to be kept relatively free of noisy digital signals often present on the system dv dd line. however, though you can power av dd and dv dd from two separate supplies if desired, you must ensure that they remain within 0.3 v of one another at all times in order to avoid damaging the chip (as per the absolute maximum ratings section). therefore, it is recom- mended that unless av dd and dv dd are connected directly together, you connect back-to-back schottky diodes between them as shown in figure 60. dv dd aduc832 agnd av dd 0.1 f 10 f analog supply 10 f dgnd 0.1 f digital supply + + figure 60. external dual-supply connections as an alternative to providing two separate power supplies, the user can help keep av dd quiet by placing a small series resistor and/or ferrite bead between it and dv dd , and then decoupling av dd separately to ground. an example of this configuration is shown in figure 61. with this configuration other analog circuitry (such as op amps, voltage reference, and so on) can be powered from the av dd supply line as well. the user will still want to include back-to-back schottky diodes between av dd and dv dd in order to protect from power-up and power-down transient condi- tions that could separate the two supply voltages momentarily. dv dd aduc832 agnd 0.1 f 10 f dgnd 0.1 f + digital supply 10 f 1.6 bead av dd figure 61. external single-supply connections notice that in both figure 60 and figure 61, a large value (10 m f) reservoir capacitor sits on dv dd and a separate 10 m f capacitor sits on av dd . also, local small-value (0.1 m f) capacitors are located at each v dd pin of the chip. as per standard design prac- tice, be sure to include all of these capacitors, and ensure the smaller capacitors are close to each av dd pin with trace lengths as short as possible. connect the ground terminal of each of these capacitors directly to the underlying ground plane. finally, it should also be noted that, at all times, the analog and digital ground pins on the aduc832 must be referenced to the same system ground reference point. power consumption the currents consumed by the various sections of the aduc832 are shown in table xxxiv. the core values given represent the current drawn by dv dd , while the rest (adc, dac, voltage ref) are pulled by the av dd pin and can be disabled in software when not in use. the other on-chip peripherals (watchdog timer, power supply monitor, and so on) consume negligible current and are therefore lumped in with the core operating current here. of course, the user must add any currents sourced by the parallel and serial i/o pins, and sourced by the dac, in order to deter- mine the total current needed at the aduc832 s supply pins. also, current drawn from the dv dd supply will increase by approximately 10 ma during flash/ee erase and program cycles. table xxxiv. typical i dd of core and peripherals v dd = 5 v v dd = 3 v core: (normal mode) (1.6 nas m clk ) + (0.8 nas m clk ) + 6 ma 3 ma core: (idle mode) (0.75 nas m clk ) + (0.25 nas m clk ) + 5 ma 3 ma adc: 1.3 ma 1.0 ma dac (each): 250 m a 200 m a voltage ref: 200 m a 150 m a since operating dv dd current is primarily a function of clock speed, the expressions for core supply current in table xxxiv are given as functions of m clk , the core clock frequency. plug in a value for m clk in hertz to determine the current consumed by the core at that oscillator frequency. since the adc and dacs can be enabled or disabled in software, add only the currents from the peripherals you expect to use. and again, do not forget to include current sourced by i/o pins, serial port pins, dac outputs, and so forth, plus the additional current drawn during flash/ee erase and program cycles. a software switch allows the chip to be switched from normal mode into idle mode, and also into full power-down mode. below are brief descriptions of power-down and idle modes. power saving modes in idle mode, the oscillator continues to run but the core clock generated from the pll is halted. the on-chip peripherals continue to receive the clock, and remain functional. the cpu status is preserved with the stack pointer and program counter, and all other internal registers maintain their data during idle mode. port pins and dac output pins retain their states in this mode. the chip will recover from idle mode upon receiving any enabled interrupt, or upon receiving a hardware reset. in full power-down mode, both the pll and the clock to the core are stopped. the on-chip oscillator can be halted or can continue to oscillate depending on the state of the oscillator power-down bit in the pllcon sfr. the tic, being driven directly from rev. 0 e64e aduc832 the oscillator, can also be enabled during power down. all other on-chip peripherals however, are shut down. port pins retain their logic levels in this mode, but the dac output goes to a high impedance state (three-state). during full power-down mode, the aduc832 consumes a total of approximately 20 asserting the reset pin (pin 15) returns to normal mode. all registers are set to their default state a nd program execution starts at the reset vector once the reset pin is deasserted. cycling power all registers are set to their default state and program execution starts at the reset vector approximately 128 ms later. time interval counter (tic) interrupt power-down mode is terminated and the cpu services the tic interrupt. the reti at the end of the tic isr will return the core to the instruction after the one that enabled power-down. i 2 c or spi interrupt power-down mode is terminated and the cpu services the i 2 c/spi interrupt. the reti at the end of the isr will return the core to the instruction after the one that enabled power-down. it should be noted that the i 2 c/spi power-down interrupt enable bit (seripd) in the pcon sfr must first be set to allow this mode of operation. int0 interrupt power-down mode is terminated and the cpu services the int0 interrupt. the reti at the end of the isr will return the core to the instruction after the one that enabled power-down. the int0 pin must not be driven low during or within 2 machine cycles of the instruction that initiates power-down mode. it should be noted that the int0 power-down interrupt enable bit (int0pd) in the pcon sfr must first be set to allow this mode of operation. power-on reset an internal por (power-on reset) is implemented on the aduc832. for dv dd below 2.45 v, the internal por will hold the aduc832 in reset. as dv dd rises above 2.45 v, an internal timer will timeout for 128 ms approximately before the part is released from reset. the user must ensure that the power supply has reached a stable 2.7 v minimum level by this time. likewise on power-down, the internal por will hold the aduc832 in reset until the power supply has dropped below 1 v. figure 62 illustrates the operation of the internal por in detail. 128ms typ 1.0v typ 128ms typ 2.45v typ 1.0v typ internal core reset dv dd figure 62. internal por operation grounding and board layout recommendations as with all high resolution data converters, special attention must be paid to grounding and pc board layout of aduc832- based designs in order to achieve optimum performance from the adc and dacs. although the aduc832 has separate pins for analog and digital ground (agnd and dgnd), the user must not tie these to two separate ground planes unless the two ground planes are connected together very close to the aduc832, as illustrated in the simpli- fied example of figure 63a. in systems where digital and analog ground planes are connected together somewhere else (at the system ? s power supply for example), they cannot be connected again near the aduc832 since a ground loop would result. in these cases, tie the aduc832 ? s agnd and dgnd pins all to the analog ground plane, as illustrated in figure 63b. in systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board such that digital return currents do not flow near analog circuitry and vice versa. the aduc832 can then be placed between the digital and analog sections, as illustrated in figure 63c. in all of these scenarios, and in more complicated real-life appli- cations, keep in mind the flow of current from the supplies and back to ground. make sure the return paths for all currents are as close as possible to the paths the currents took to reach their desti- nations. for example, do not power components on the analog side of figure 63b with dv dd since that would force return currents from dv dd to flow through agnd. also, try to avoid digital currents flowing under analog circuitry, which could happen if the user placed a noisy digital chip on the left half of the board in figure 63c. whenever possible, avoid large discontinuities in the ground plane(s) (such as are formed by a long trace on the same layer), since they force return signals to travel a longer path. and of course, make all connections to the ground plane directly, with little or no trace separating the pin from its via to ground. if the user plans to connect fast logic signals (rise/fall time < 5 ns) to any of the aduc832 ? s digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at the aduc832 input pins. a value of 100 ? ? b. dgnd agnd pl ace analog comp onents here pl ace digital comp onents here c. gnd pl ace analog comp onents here pl ace digital comp onents here a. pl ace analog comp onents here pl ace digital comp onents here dgnd agnd figure 63. system grounding schemes rev. 0 aduc832 ?5 other hardware considerations to facilitate in-circuit programming, plus in-circuit debug and emulation options, users will want to implement some simple connection points in their hardware that will allow easy access to download, debug, and emulation modes. in-circuit serial download access nearly all aduc832 designs will want to take advantage of the in-circuit reprogrammability of the chip. this is accomplished by a connection to the aduc832 s uart, which requires an external rs-232 chip for level translation if downloading code from a pc. basic configuration of an rs-232 connection is illustrated in figure 64 with a simple adm202-based circuit. if users would rather not design an rs-232 chip onto a board, refer to the application note uc006 C a 4-wire uart-to-pc interface * for a simple (and zero-cost-per-board) method of gaining in-circuit serial download access to the aduc832. in addition to the basic uart connections, users will also need a way to trigger the chip into download mode. this is accomplished via a 1 k ? pull-down resistor that can be jumpered onto the psen pin, as shown in figure 64. to get the aduc832 into download mode, simply connect this jumper and power-cycle the device (or manually reset the device, if a manual reset button is available) and it will be ready to receive a new program serially. with the jumper removed, the device will come up in normal mode (and run the program) whenever power is cycled or reset is toggled. note that psen is normally an output (as described in the external memory interface section) and is sampled as an input only on the falling edge of reset (i.e., at power-up or upon an external manual reset). note also that if any external circuitry unintentionally pulls psen low during power-up or reset events, it could cause the chip to enter download mode and therefore fail to begin user code execution as it should. to prevent this, ensure that no external signals are capable of pulling the psen pin low, except for the external psen jumper itself. * application note uc006 is available at www.analog.com/microconverter c1+ v+ c1 c2+ c2 v t2out r2in v cc gnd t1out r1in r1out t1in t2in r2out adm202 dv dd 27 34 33 31 30 29 28 39 38 37 36 35 32 40 47 46 44 43 42 41 52 51 50 49 48 45 dv dd 1k dv dd 1k 2-pin header for emulation access (normally open) download/debug enable jumper (normally open) 32.768khz dv dd 1 9-pin d-sub female 2 3 4 5 6 7 8 9 av dd av dd agnd c ref v ref dac0 dac1 dv dd dgnd psen dgnd dv dd xtal2 xtal1 reset rxd txd dv dd dgnd not connected in this example dv dd aduc832 dac output v ref output adc0 adc7 analog input 10 14 16 19 18 20 26 24 ea figure 64. example aduc832 system (pqfp package) rev. 0 e66e aduc832 windows is a registered trademark of microsoft corporation. embedded serial port debugger from a hardware perspective, entry into serial port debug mode is identical to the serial download entry sequence described above. in fact, both serial download and serial port debug modes can be thought of as essentially one mode of operation used in two different ways. note that the serial port debugger is fully contained on the aduc832 device, (unlike rom monitor type debuggers) and therefore no external memory is needed to enable in-system debug sessions. single-pin emulation mode also built into the aduc832 is a dedicated controller for single-pin in-circuit emulation (ice) using standard production aduc832 devices. in this mode, emulation access is gained by connection to a single pin, the ea pin. normally, this pin is hardwired either high or low to select execution from internal or external program memory space, as described earlier. to enable single-pin emulation mode, however, users will need to pull the ea pin high through a 1 k ? (), () , , ( ) , , ( ) ( ) () , , , , , , , rev. 0 aduc832 e67e timing specifications 1, 2, 3 (av dd = 2.7 v to 3.6 v or 4.75 v to 5.25 v, dv dd = 2.7 v to 3.6 v or 4.75 v to 5.25 v; all specifications t min to t max , unless otherwise noted.) 32.768 khz external crystal parameter min typ max unit figure clock input (external clock driven xtal1) t ck xtal1 period 30.52 , , , = , ( ) , + + + ( ) rev. 0 e68e aduc832 16.78 mhz core clk variable clock parameter min max min max unit figure external program memory read cycle t lhll ale pulsewidth 79 2t ck ? 40 ns 70 t avll address valid to ale low 19 t ck ? 40 ns 70 t llax address hold after ale low 29 t ck ? 30 ns 70 t lliv ale low to valid instruction in 138 4t ck ? 100 ns 70 t llpl ale low to psen low 29 t ck ? 30 ns 70 t plph psen pulsewidth 133 3t ck ? 45 ns 70 t pliv psen low to valid instruction in 73 3t ck ? 105 ns 70 t pxix input instruction hold after psen 00ns70 t pxiz input instruction float after psen 34 t ck ? 25 ns 70 t aviv address to valid instruction in 193 5t ck ? 105 ns 70 t plaz psen low to address float 25 25 ns 70 t phax address hold after psen h igh 0 0 ns 70 m clk ale (o) psen o port0i/o porto av p pp iv piv pa a pi pi pa aviv pcot instrction in pc 0 eprc rev. 0 aduc832 e69e 16.78 mhz core clk variable clock parameter min max min max unit figure external data memory read cycle t rlrh rd pulsewidth 257 6t ck ? 100 ns 71 t avll address valid after ale low 19 t ck ? 40 ns 71 t llax address hold after ale low 24 t ck ? 35 ns 71 t rldv rd low to valid data in 133 5t ck ? 165 ns 71 t rhdx data and address hold after rd 00 ns71 t rhdz data float after rd 49 2t ck ? 70 ns 71 t lldv ale low to valid data in 326 8t ck ? 150 ns 71 t avdv address to valid data in 371 9t ck ? 165 ns 71 t llwl ale low to rd or wr low 128 228 3t ck ? 50 3t ck +50 ns 71 t avwl address valid to rd or wr low 108 4t ck ? 130 ns 71 t rlaz rd low to address float 0 0 ns 71 t whlh rd or wr high to ale high 19 257 t ck ? 40 6t ck ? 100 ns 71 m clk ale (o) port 0 (i/o) port 2 (o) t whlh t lldv t llwl t rlrh t avwl t llax t avll t rlaz t rhdx t rhdz t avdv a0ea7 (out) data (in) a16ea23 a8ea15 t rldv psen o rd o 1 edrc rev. 0 e70e aduc832 16.78 mhz core clk variable clock parameter min max min max unit figure external data memory write cycle t wlwh wr pulsewidth 257 6t ck ? 100 ns 72 t avll address valid after ale low 19 t ck ? 40 ns 72 t llax address hold after ale low 24 t ck ? 35 ns 72 t llwl ale low to rd or wr low 128 228 3t ck ? 50 3t ck +50 ns 72 t avwl address valid to rd or wr low 108 4t ck ? 130 ns 72 t qvwx data valid to wr transition 9 t ck ? 50 ns 72 t qvwh data setup before wr 267 7t ck ? 150 ns 72 t whqx data and address hold after wr 9t ck ? 50 ns 72 t whlh rd or wr high to ale high 19 257 t ck ? 40 6t ck ? 100 ns 72 m clk ale (o) port 2 (o) t whlh t wlwh t llwl t avwl t llax t avll t qvwx t qvwh t whqx a0ea7 data a16ea23 a8ea15 psen o wr o edwc rev. 0 aduc832 e71e 16.78 mhz core clk variable clock parameter min typ max min typ max unit figure uart timing (shift register mode) t xlxl serial port clock cycle time 715 12t ck + () ( ) ( ) ( ) rev. 0 e72e aduc832 parameter min max unit figure i 2 c compatible interface timing t l sclock low pulsewidth 4.7 () () () rev. 0 aduc832 e73e parameter min typ max unit figure spi master mode timing (cpha = 1) t sl sclock low pulsewidth * 476 ns 75 t sh sclock high pulsewidth * 476 ns 75 t dav data output valid after sclock edge 50 ns 75 t dsu data input setup time before sclock edge 100 ns 75 t dhd data input hold time after sclock edge 100 ns 75 t df data output fall time 10 25 ns 75 t dr data output rise time 10 25 ns 75 t sr sclock rise time 10 25 ns 75 t sf sclock fall time 10 25 ns 75 * characterized under the following conditions: a. core clock divider bits cd2, cd1, and cd0 bits in pllcon sfr set to 0, 1, and 1 respectively, i.e., core clock frequency = 2. 09 mhz and b. spi bit-rate selection bits spr1 and spr0 bits in spicon sfr set to 0 and 0 respectively. mosi sclock (cpo l = 1) sclock (cpo l = 0) t sh t sl t sr t sf bit 6 e 1 lsb in t dr miso t dav t df t dsu msb bit 6 e 1 lsb t dhd msb in figure 75. spi master mode timing (cpha = 1) rev. 0 e74e aduc832 parameter min typ max unit figure spi master mode timing (cpha = 0) t sl sclock low pulsewidth * 476 ns 76 t sh sclock high pulsewidth * 476 ns 76 t dav data output valid after sclock edge 50 ns 76 t dosu data output setup before sclock edge 150 ns 76 t dsu data input setup time before sclock edge 100 ns 76 t dhd data input hold time after sclock edge 100 ns 76 t df data output fall time 10 25 ns 76 t dr data output rise time 10 25 ns 76 t sr sclock rise time 10 25 ns 76 t sf sclock fall time 10 25 ns 76 * characterized under the following conditions: a. core clock divider bits cd2, cd1, and cd0 bits in pllcon sfr set to 0, 1, and 1 respectively, i.e., core clock frequency = 2. 09 mhz and b. spi bit-rate selection bits spr1 and spr0 bits in spicon sfr set to 0 and 0 respectively. t dav miso mosi sclock (cpo l = 1) sclock (cpo l = 0) t sh t sl t sr t sf t dosu t df t dr t dsu t dhd msb bit 6 e 1 lsb bit 6 e 1 lsb in msb in figure 76. spi master mode timing (cpha = 0) rev. 0 aduc832 e75e parameter min typ max unit figure spi slave mode timing (cpha = 1) t ss ss to sclock edge 0 ns 77 t sl sclock low pulsewidth 330 ns 77 t sh sclock high pulsewidth 330 ns 77 t dav data output valid after sclock edge 50 ns 77 t dsu data input setup time before sclock edge 100 ns 77 t dhd data input hold time after sclock edge 100 ns 77 t df data output fall time 10 25 ns 77 t dr data output rise time 10 25 ns 77 t sr sclock rise time 10 25 ns 77 t sf sclock fall time 10 25 ns 77 t sfs ss high after sclock edge 0 ns 77 miso mosi sclock (cpo l = 1) sclock (cpo l = 0) t sh t sr t sf t dav t df t dr msb lsb t sfs t ss ss it1 it1 s sin sin ds dd spistcpa1 rev. 0 e76e aduc832 parameter min typ max unit figure spi slave mode timing (cpha = 0) t ss ss to sclock edge 0 ns 78 t sl sclock low pulsewidth 330 ns 78 t sh sclock high pulsewidth 330 ns 78 t dav data output valid after sclock edge 50 ns 78 t dsu data input setup time before sclock edge 100 ns 78 t dhd data input hold time after sclock edge 100 ns 78 t df data output fall time 10 25 ns 78 t dr data output rise time 10 25 ns 78 t sr sclock rise time 10 25 ns 78 t sf sclock fall time 10 25 ns 78 t doss data output valid after ss e dge 20 ns 78 t sfs ss high after sclock edge ns 78 t dav t sfs miso mosi sclock (cpo l = 1) sclock (cpo l = 0) t sh t sl t sr t df t dr t dsu t dhd t ss t doss msb bit 6e1 lsb bit 6e1 lsb in msb in t sf ss spistcpa0 rev. 0 aduc832 e77e outline dimensions 52-lead plastic quad flatpack [mqfp] (s-52) dimensions shown in millimeters seating plane view a 0.23 0.11 2.45 max 1.03 0.88 0.73 top view (pins down) 1 39 40 13 14 27 26 52 pin 1 0.65 bsc 14.15 13.90 sq 13.65 7.80 ref 10.20 10.00 sq 9.80 0.38 0.22 view a rotated 90 ccw 7 0 2.10 2.00 1.95 0.10 min coplanarity compliant to jedec standards mo-112-ac-1 56-lead frame chip scale package [lfcsp] 8 8 mm body (cp-56) dimensions shown in millimeters pin 1 indicator top view 7.75 bsc sq 8.00 bsc sq 1 56 14 15 43 42 28 29 bottom view 6.25 6.10 5.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.25 ref 0.70 max 0.65 nom 1.00 0.90 0.80 6.50 ref seating plane 0.10 max 0.60 max 0.60 max pin 1 indicator compliant to jedec standards mo-220-vlld-2 coplanarity 0.08 e78e e79e c02987e0e11/02(0) printed in u.s.a. e80e |
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